diff options
Diffstat (limited to 'plugins/arm/v7/opdefs/mvn_A88116.d')
-rw-r--r-- | plugins/arm/v7/opdefs/mvn_A88116.d | 114 |
1 files changed, 90 insertions, 24 deletions
diff --git a/plugins/arm/v7/opdefs/mvn_A88116.d b/plugins/arm/v7/opdefs/mvn_A88116.d index 1f3f390..38ef06e 100644 --- a/plugins/arm/v7/opdefs/mvn_A88116.d +++ b/plugins/arm/v7/opdefs/mvn_A88116.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,28 @@ @title MVN (register) -@desc Bitwise NOT (register) writes the bitwise inverse of a register value to the destination register. It can optionally update the condition flags based on the result. +@id 115 + +@desc { + + Bitwise NOT (register) writes the bitwise inverse of a register value to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (t1) { @half 0 1 0 0 0 0 1 1 1 1 Rm(3) Rd(3) - @syntax "mvns" <reg_D> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_M = Register(Rm) + } + + @asm mvn reg_D reg_M } @@ -44,21 +54,43 @@ @word 1 1 1 0 1 0 1 0 0 1 1 S(1) 1 1 1 1 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) - @syntax <reg_D> <reg_M> <?shift> + @syntax { + + @assert { + + S == 0 + + } - @conv { + @conv { - reg_D = Register(Rd) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm3:imm2) + reg_D = Register(Rd) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } + + @asm mvn.w reg_D reg_M ?shift } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") + @asm mvns.w reg_D reg_M ?shift } @@ -68,21 +100,55 @@ @word cond(4) 0 0 0 1 1 1 1 S(1) 0 0 0 0 Rd(4) imm5(5) type(2) 0 Rm(4) - @syntax <reg_D> <reg_M> <?shift> + @syntax { - @conv { + @assert { - reg_D = Register(Rd) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm5) + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm mvn reg_D reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm mvns reg_D reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } |