diff options
Diffstat (limited to 'plugins/arm/v7/opdefs/sbc_A88162.d')
-rw-r--r-- | plugins/arm/v7/opdefs/sbc_A88162.d | 121 |
1 files changed, 95 insertions, 26 deletions
diff --git a/plugins/arm/v7/opdefs/sbc_A88162.d b/plugins/arm/v7/opdefs/sbc_A88162.d index b6e660a..1ba7592 100644 --- a/plugins/arm/v7/opdefs/sbc_A88162.d +++ b/plugins/arm/v7/opdefs/sbc_A88162.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,29 @@ @title SBC (register) -@desc Subtract with Carry (register) subtracts an optionally-shifted register value and the value of NOT (Carry flag) from a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. +@id 161 + +@desc { + + Subtract with Carry (register) subtracts an optionally-shifted register value and the value of NOT (Carry flag) from a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (t1) { @half 0 1 0 0 0 0 0 1 1 0 Rm(3) Rdn(3) - @syntax "sbcs" <reg_DN> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rdn) + reg_N = Register(Rdn) + reg_M = Register(Rm) - reg_DN = Register(Rdn) - reg_M = Register(Rm) + } + + @asm sbc ?reg_D reg_N reg_M } @@ -44,22 +55,45 @@ @word 1 1 1 0 1 0 1 1 0 1 1 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <?shift> + @syntax { + + @assert { + + S == 0 + + } - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm3:imm2) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } + + @asm sbc.w ?reg_D reg_N reg_M ?shift } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") + @asm sbcs.w ?reg_D reg_N reg_M ?shift } @@ -69,22 +103,57 @@ @word cond(4) 0 0 0 0 1 1 0 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <?shift> + @syntax { - @conv { + @assert { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm5) + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm sbc ?reg_D reg_N reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm sbcs ?reg_D reg_N reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } |