diff options
Diffstat (limited to 'plugins/arm/v7/opdefs/smull_A88189.d')
-rw-r--r-- | plugins/arm/v7/opdefs/smull_A88189.d | 81 |
1 files changed, 63 insertions, 18 deletions
diff --git a/plugins/arm/v7/opdefs/smull_A88189.d b/plugins/arm/v7/opdefs/smull_A88189.d index 5ab1c54..c0a186e 100644 --- a/plugins/arm/v7/opdefs/smull_A88189.d +++ b/plugins/arm/v7/opdefs/smull_A88189.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title SMULL -@desc Signed Multiply Long multiplies two 32-bit signed values to produce a 64-bit result. In ARM instructions, the condition flags can optionally be updated based on the result. Use of this option adversely affects performance on many processor implementations. +@id 188 + +@desc { + + Signed Multiply Long multiplies two 32-bit signed values to produce a 64-bit result. In ARM instructions, the condition flags can optionally be updated based on the result. Use of this option adversely affects performance on many processor implementations. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 1 1 0 0 0 Rn(4) RdLo(4) RdHi(4) 0 0 0 0 Rm(4) - @syntax <reg_DLO> <reg_DHI> <reg_N> <reg_M> + @syntax { + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) - @conv { + } - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) + @asm smull reg_DLO reg_DHI reg_N reg_M } @@ -46,22 +56,57 @@ @word cond(4) 0 0 0 0 1 1 0 S(1) RdHi(4) RdLo(4) Rm(4) 1 0 0 1 Rn(4) - @syntax <reg_DLO> <reg_DHI> <reg_N> <reg_M> + @syntax { + + @assert { + + S == 0 + + } + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } - @conv { + @asm smull reg_DLO reg_DHI reg_N reg_M - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smulls reg_DLO reg_DHI reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } |