diff options
Diffstat (limited to 'plugins/arm/v7/opdefs/tst_A88240.d')
-rw-r--r-- | plugins/arm/v7/opdefs/tst_A88240.d | 40 |
1 files changed, 27 insertions, 13 deletions
diff --git a/plugins/arm/v7/opdefs/tst_A88240.d b/plugins/arm/v7/opdefs/tst_A88240.d index 0ff5121..50c0507 100644 --- a/plugins/arm/v7/opdefs/tst_A88240.d +++ b/plugins/arm/v7/opdefs/tst_A88240.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,28 @@ @title TST (immediate) -@desc Test (immediate) performs a bitwise AND operation on a register value and an immediate value. It updates the condition flags based on the result, and discards the result. +@id 239 + +@desc { + + Test (immediate) performs a bitwise AND operation on a register value and an immediate value. It updates the condition flags based on the result, and discards the result. + +} @encoding (T1) { @word 1 1 1 1 0 i(1) 0 0 0 0 0 1 Rn(4) 0 imm3(3) 1 1 1 1 imm8(8) - @syntax <reg_N> <imm32> + @syntax { + + @conv { - @conv { + reg_N = Register(Rn) + const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) - reg_N = Register(Rn) - imm32 = ThumbExpandImm_C(i:imm3:imm8, 0) + } + + @asm tst reg_N const } @@ -44,18 +54,22 @@ @word cond(4) 0 0 1 1 0 0 0 1 Rn(4) 0 0 0 0 imm12(12) - @syntax <reg_N> <imm32> + @syntax { - @conv { + @conv { - reg_N = Register(Rn) - imm32 = ARMExpandImm_C(imm12, 0) + reg_N = Register(Rn) + const = ARMExpandImm_C(imm12, APSR_C) - } + } + + @asm tst reg_N const + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } |