diff options
Diffstat (limited to 'plugins')
23 files changed, 1896 insertions, 38 deletions
diff --git a/plugins/arm/v7/opcodes/opcodes_tmp_arm.h b/plugins/arm/v7/opcodes/opcodes_tmp_arm.h index 4106cbd..0e686e1 100644 --- a/plugins/arm/v7/opcodes/opcodes_tmp_arm.h +++ b/plugins/arm/v7/opcodes/opcodes_tmp_arm.h @@ -19,10 +19,6 @@ #define armv7_read_arm_instr_msr_immediate_b9(r) NULL #define armv7_read_arm_instr_msr_register_a8(r) NULL #define armv7_read_arm_instr_msr_register_b9(r) NULL -#define armv7_read_arm_instr_pkh(r) NULL -#define armv7_read_arm_instr_pld_literal(r) NULL -#define armv7_read_arm_instr_pld_pldw_immediate(r) NULL -#define armv7_read_arm_instr_pld_pldw_register(r) NULL #define armv7_read_arm_instr_pli_immediate_literal(r) NULL #define armv7_read_arm_instr_pli_register(r) NULL #define armv7_read_arm_instr_rfe(r) NULL @@ -32,25 +28,11 @@ #define armv7_read_arm_instr_smlawb_smlawt(r) NULL #define armv7_read_arm_instr_smulbb_smulbt_smultb_smultt(r) NULL #define armv7_read_arm_instr_smulwb_smulwt(r) NULL -#define armv7_read_arm_instr_smusd(r) NULL #define armv7_read_arm_instr_srs_arm(r) NULL -#define armv7_read_arm_instr_ssat(r) NULL -#define armv7_read_arm_instr_ssat16(r) NULL -#define armv7_read_arm_instr_ssax(r) NULL -#define armv7_read_arm_instr_ssub16(r) NULL -#define armv7_read_arm_instr_ssub8(r) NULL #define armv7_read_arm_instr_stc_stc2(r) NULL #define armv7_read_arm_instr_stmda_stmed(r) NULL #define armv7_read_arm_instr_stmdb_stmfd(r) NULL #define armv7_read_arm_instr_stmib_stmfa(r) NULL #define armv7_read_arm_instr_stm_stmia_stmea(r) NULL #define armv7_read_arm_instr_stm_user_registers(r) NULL -#define armv7_read_arm_instr_sub_register_shifted_register(r) NULL -#define armv7_read_arm_instr_sxtab(r) NULL -#define armv7_read_arm_instr_sxtab16(r) NULL -#define armv7_read_arm_instr_sxtah(r) NULL -#define armv7_read_arm_instr_sxtb(r) NULL -#define armv7_read_arm_instr_sxtb16(r) NULL -#define armv7_read_arm_instr_sxth(r) NULL -#define armv7_read_arm_instr_wfe(r) NULL #endif diff --git a/plugins/arm/v7/opcodes/opcodes_tmp_thumb_16.h b/plugins/arm/v7/opcodes/opcodes_tmp_thumb_16.h index 1968037..62235ec 100644 --- a/plugins/arm/v7/opcodes/opcodes_tmp_thumb_16.h +++ b/plugins/arm/v7/opcodes/opcodes_tmp_thumb_16.h @@ -4,7 +4,4 @@ #define armv7_read_thumb_16_instr_it(r) NULL #define armv7_read_thumb_16_instr_ldm_ldmia_ldmfd_thumb(r) NULL #define armv7_read_thumb_16_instr_stm_stmia_stmea(r) NULL -#define armv7_read_thumb_16_instr_sxtb(r) NULL -#define armv7_read_thumb_16_instr_sxth(r) NULL -#define armv7_read_thumb_16_instr_wfe(r) NULL #endif diff --git a/plugins/arm/v7/opcodes/opcodes_tmp_thumb_32.h b/plugins/arm/v7/opcodes/opcodes_tmp_thumb_32.h index 1ed547c..4848c92 100644 --- a/plugins/arm/v7/opcodes/opcodes_tmp_thumb_32.h +++ b/plugins/arm/v7/opcodes/opcodes_tmp_thumb_32.h @@ -15,11 +15,7 @@ #define armv7_read_thumb_32_instr_mrs_banked_register(r) NULL #define armv7_read_thumb_32_instr_msr_banked_register(r) NULL #define armv7_read_thumb_32_instr_msr_register(r) NULL -#define armv7_read_thumb_32_instr_pkh(r) NULL #define armv7_read_thumb_32_instr_pld_immediate(r) NULL -#define armv7_read_thumb_32_instr_pld_literal(r) NULL -#define armv7_read_thumb_32_instr_pld_pldw_immediate(r) NULL -#define armv7_read_thumb_32_instr_pld_pldw_register(r) NULL #define armv7_read_thumb_32_instr_pld_register(r) NULL #define armv7_read_thumb_32_instr_pli_immediate_literal(r) NULL #define armv7_read_thumb_32_instr_pli_register(r) NULL @@ -30,7 +26,6 @@ #define armv7_read_thumb_32_instr_smlawb_smlawt(r) NULL #define armv7_read_thumb_32_instr_smulbb_smulbt_smultb_smultt(r) NULL #define armv7_read_thumb_32_instr_smulwb_smulwt(r) NULL -#define armv7_read_thumb_32_instr_smusd(r) NULL #define armv7_read_thumb_32_instr_sqadd16(r) NULL #define armv7_read_thumb_32_instr_sqadd8(r) NULL #define armv7_read_thumb_32_instr_sqasx(r) NULL @@ -38,22 +33,10 @@ #define armv7_read_thumb_32_instr_sqsub16(r) NULL #define armv7_read_thumb_32_instr_sqsub8(r) NULL #define armv7_read_thumb_32_instr_srs_thumb(r) NULL -#define armv7_read_thumb_32_instr_ssat(r) NULL -#define armv7_read_thumb_32_instr_ssat16(r) NULL -#define armv7_read_thumb_32_instr_ssax(r) NULL -#define armv7_read_thumb_32_instr_ssub16(r) NULL -#define armv7_read_thumb_32_instr_ssub8(r) NULL #define armv7_read_thumb_32_instr_stc_stc2(r) NULL #define armv7_read_thumb_32_instr_stmdb_stmfd(r) NULL #define armv7_read_thumb_32_instr_stm_stmia_stmea(r) NULL #define armv7_read_thumb_32_instr_sub_register_thumb(r) NULL #define armv7_read_thumb_32_instr_subs_pc_lr_thumb(r) NULL -#define armv7_read_thumb_32_instr_sxtab(r) NULL -#define armv7_read_thumb_32_instr_sxtab16(r) NULL -#define armv7_read_thumb_32_instr_sxtah(r) NULL -#define armv7_read_thumb_32_instr_sxtb(r) NULL -#define armv7_read_thumb_32_instr_sxtb16(r) NULL -#define armv7_read_thumb_32_instr_sxth(r) NULL #define armv7_read_thumb_32_instr_tbb_tbh(r) NULL -#define armv7_read_thumb_32_instr_wfe(r) NULL #endif diff --git a/plugins/arm/v7/opdefs/Makefile.am b/plugins/arm/v7/opdefs/Makefile.am index 0538359..40ab737 100644 --- a/plugins/arm/v7/opdefs/Makefile.am +++ b/plugins/arm/v7/opdefs/Makefile.am @@ -146,6 +146,10 @@ ARMV7_DEFS = \ orr_A88122.d \ orr_A88123.d \ orr_A88124.d \ + pkh_A88125.d \ + pld_A88126.d \ + pld_A88127.d \ + pld_A88128.d \ pop_A88131.d \ pop_A88132.d \ push_A88133.d \ @@ -199,6 +203,12 @@ ARMV7_DEFS = \ smmul_A88186.d \ smuad_A88187.d \ smull_A88189.d \ + smusd_A88191.d \ + ssat_A88193.d \ + ssat16_A88194.d \ + ssax_A88195.d \ + ssub16_A88196.d \ + ssub8_A88197.d \ str_A88203.d \ str_A88204.d \ str_A88205.d \ @@ -220,9 +230,17 @@ ARMV7_DEFS = \ sub_A88221.d \ sub_A88222.d \ sub_A88223.d \ + sub_A88224.d \ sub_A88225.d \ + sub_A88226.d \ svc_A88228.d \ swp_A88229.d \ + sxtab_A88230.d \ + sxtab16_A88231.d \ + sxtah_A88232.d \ + sxtb_A88233.d \ + sxtb16_A88234.d \ + sxth_A88235.d \ teq_A88237.d \ teq_A88238.d \ teq_A88239.d \ @@ -263,6 +281,7 @@ ARMV7_DEFS = \ uxtb_A88274.d \ uxtb16_A88275.d \ uxth_A88276.d \ + wfe_A88424.d \ wfi_A88425.d \ yield_A88426.d diff --git a/plugins/arm/v7/opdefs/pkh_A88125.d b/plugins/arm/v7/opdefs/pkh_A88125.d new file mode 100644 index 0000000..5c2411e --- /dev/null +++ b/plugins/arm/v7/opdefs/pkh_A88125.d @@ -0,0 +1,141 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title PKH + +@id 124 + +@desc { + + Pack Halfword combines one halfword of its first operand with the other halfword of its shifted second operand. + +} + +@encoding (T1) { + + @word 1 1 1 0 1 0 1 0 1 1 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) tb(1) T(1) Rm(4) + + @syntax { + + @assert { + + tb == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(tb:'0', imm3:imm2) + + } + + @asm pkhbt ?reg_D reg_N reg_M ?shift + + } + + @syntax { + + @assert { + + tb == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(tb:'0', imm3:imm2) + + } + + @asm pkhtb ?reg_D reg_N reg_M ?shift + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 1 0 0 0 Rn(4) Rd(4) imm5(5) tb(1) 0 1 Rm(4) + + @syntax { + + @assert { + + tb == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(tb:'0', imm5) + + } + + @asm pkhbt ?reg_D reg_N reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @assert { + + tb == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(tb:'0', imm5) + + } + + @asm pkhtb ?reg_D reg_N reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/pld_A88126.d b/plugins/arm/v7/opdefs/pld_A88126.d new file mode 100644 index 0000000..be5f348 --- /dev/null +++ b/plugins/arm/v7/opdefs/pld_A88126.d @@ -0,0 +1,171 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title PLD, PLDW (immediate) + +@id 125 + +@desc { + + Preload Data signals the memory system that data memory accesses from a specified address are likely in the near future. The memory system can respond by taking actions that are expected to speed up the memory accesses when they do occur, such as pre-loading the cache line containing the specified address into the data cache. On an architecture variant that includes both the PLD and PLDW instructions, the PLD instruction signals that the likely memory access is a read, and the PLDW instruction signals that it is a write. The effect of a PLD or PLDW instruction is IMPLEMENTATION DEFINED. For more information, see Preloading caches on page A3-157 and Behavior of Preload Data (PLD, PLDW) and Preload Instruction (PLI) with caches on page B2-1269. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 0 0 1 0 W(1) 1 Rn(4) 1 1 1 1 imm12(12) + + @syntax { + + @assert { + + W == 0 + + } + + @conv { + + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm pld maccess + + } + + @syntax { + + @assert { + + W == 1 + + } + + @conv { + + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm pldw maccess + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 0 0 0 0 0 W(1) 1 Rn(4) 1 1 1 1 1 1 0 0 imm8(8) + + @syntax { + + @assert { + + W == 0 + + } + + @conv { + + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm pld maccess + + } + + @syntax { + + @assert { + + W == 1 + + } + + @conv { + + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm pldw maccess + + } + +} + +@encoding (A1) { + + @word 1 1 1 1 0 1 0 1 U(1) R(1) 0 1 Rn(4) 1 1 1 1 imm12(12) + + @syntax { + + @assert { + + R == 1 + + } + + @conv { + + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm pld maccess + + } + + @syntax { + + @assert { + + R == 0 + + } + + @conv { + + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm pldw maccess + + } + +} + diff --git a/plugins/arm/v7/opdefs/pld_A88127.d b/plugins/arm/v7/opdefs/pld_A88127.d new file mode 100644 index 0000000..12d7942 --- /dev/null +++ b/plugins/arm/v7/opdefs/pld_A88127.d @@ -0,0 +1,69 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title PLD (literal) + +@id 126 + +@desc { + + Preload Data signals the memory system that data memory accesses from a specified address are likely in the near future. The memory system can respond by taking actions that are expected to speed up the memory accesses when they do occur, such as pre-loading the cache line containing the specified address into the data cache. The effect of a PLD instruction is IMPLEMENTATION DEFINED. For more information, see Preloading caches on page A3-157 and Behavior of Preload Data (PLD, PLDW) and Preload Instruction (PLI) with caches on page B2-1269. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 0 0 U(1) 0 0 1 1 1 1 1 1 1 1 1 imm12(12) + + @syntax { + + @conv { + + imm32 = ZeroExtend(imm12, 32) + + } + + @asm pld imm32 + + } + +} + +@encoding (A1) { + + @word 1 1 1 1 0 1 0 1 U(1) 1 0 1 1 1 1 1 1 1 1 1 imm12(12) + + @syntax { + + @conv { + + imm32 = ZeroExtend(imm12, 32) + + } + + @asm pld imm32 + + } + +} + diff --git a/plugins/arm/v7/opdefs/pld_A88128.d b/plugins/arm/v7/opdefs/pld_A88128.d new file mode 100644 index 0000000..e12d928 --- /dev/null +++ b/plugins/arm/v7/opdefs/pld_A88128.d @@ -0,0 +1,129 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title PLD, PLDW (register) + +@id 127 + +@desc { + + Preload Data signals the memory system that data memory accesses from a specified address are likely in the near future. The memory system can respond by taking actions that are expected to speed up the memory accesses when they do occur, such as pre-loading the cache line containing the specified address into the data cache. On an architecture variant that includes both the PLD and PLDW instructions, the PLD instruction signals that the likely memory access is a read, and the PLDW instruction signals that it is a write. The effect of a PLD or PLDW instruction is IMPLEMENTATION DEFINED. For more information, see Preloading caches on page A3-157 and Behavior of Preload Data (PLD, PLDW) and Preload Instruction (PLI) with caches on page B2-1269. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 0 0 0 0 W(1) 1 Rn(4) 1 1 1 1 0 0 0 0 0 0 imm2(2) Rm(4) + + @syntax { + + @assert { + + W == 0 + + } + + @conv { + + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = FixedShift(SRType_LSL, imm2) + maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) + + } + + @asm pld maccess + + } + + @syntax { + + @assert { + + W == 1 + + } + + @conv { + + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = FixedShift(SRType_LSL, imm2) + maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) + + } + + @asm pldw maccess + + } + +} + +@encoding (A1) { + + @word 1 1 1 1 0 1 1 1 U(1) R(1) 0 1 Rn(4) 1 1 1 1 imm5(5) type(2) 0 Rm(4) + + @syntax { + + @assert { + + R == 1 + + } + + @conv { + + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) + + } + + @asm pld maccess + + } + + @syntax { + + @assert { + + R == 0 + + } + + @conv { + + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) + + } + + @asm pldw maccess + + } + +} + diff --git a/plugins/arm/v7/opdefs/smusd_A88191.d b/plugins/arm/v7/opdefs/smusd_A88191.d new file mode 100644 index 0000000..93a392c --- /dev/null +++ b/plugins/arm/v7/opdefs/smusd_A88191.d @@ -0,0 +1,137 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title SMUSD + +@id 190 + +@desc { + + Signed Multiply Subtract Dual performs two signed 16 × 16-bit multiplications. It subtracts one of the products from the other, and writes the result to the destination register. Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This produces top × bottom and bottom × top multiplication. Overflow cannot occur. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 1 0 1 0 0 Rn(4) 1 1 1 1 Rd(4) 0 0 0 M(1) Rm(4) + + @syntax { + + @assert { + + M == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smusd ?reg_D reg_N reg_M + + } + + @syntax { + + @assert { + + M == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smusdx ?reg_D reg_N reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 1 0 0 0 0 Rd(4) 1 1 1 1 Rm(4) 0 1 M(1) 1 Rn(4) + + @syntax { + + @assert { + + M == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smusd ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @assert { + + M == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smusdx ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/ssat16_A88194.d b/plugins/arm/v7/opdefs/ssat16_A88194.d new file mode 100644 index 0000000..8ad328e --- /dev/null +++ b/plugins/arm/v7/opdefs/ssat16_A88194.d @@ -0,0 +1,79 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title SSAT16 + +@id 193 + +@desc { + + Signed Saturate 16 saturates two signed 16-bit values to a selected signed range. The Q flag is set if the operation saturates. + +} + +@encoding (T1) { + + @word 1 1 1 1 0 0 1 1 0 0 1 0 Rn(4) 0 0 0 0 Rd(4) 0 0 0 0 sat_imm(4) + + @syntax { + + @conv { + + reg_D = Register(Rd) + saturate_to = UIntInc(sat_imm) + reg_N = Register(Rn) + + } + + @asm ssat16 reg_D saturate_to reg_N + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 1 0 1 0 sat_imm(4) Rd(4) 1 1 1 1 0 0 1 1 Rn(4) + + @syntax { + + @conv { + + reg_D = Register(Rd) + saturate_to = UIntInc(sat_imm) + reg_N = Register(Rn) + + } + + @asm ssat16 reg_D saturate_to reg_N + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/ssat_A88193.d b/plugins/arm/v7/opdefs/ssat_A88193.d new file mode 100644 index 0000000..def45d1 --- /dev/null +++ b/plugins/arm/v7/opdefs/ssat_A88193.d @@ -0,0 +1,81 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title SSAT + +@id 192 + +@desc { + + Signed Saturate saturates an optionally-shifted signed value to a selectable signed range. The Q flag is set if the operation saturates. + +} + +@encoding (T1) { + + @word 1 1 1 1 0 0 1 1 0 0 sh(1) 0 Rn(4) 0 imm3(3) Rd(4) imm2(2) 0 sat_imm(5) + + @syntax { + + @conv { + + reg_D = Register(Rd) + saturate_to = UIntInc(sat_imm) + reg_N = Register(Rn) + shift = DecodeImmShift(sh:'0', imm3:imm2) + + } + + @asm ssat reg_D saturate_to reg_N ?shift + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 1 0 1 sat_imm(5) Rd(4) imm5(5) sh(1) 0 1 Rn(4) + + @syntax { + + @conv { + + reg_D = Register(Rd) + saturate_to = UIntInc(sat_imm) + reg_N = Register(Rn) + shift = DecodeImmShift(sh:'0', imm5) + + } + + @asm ssat reg_D saturate_to reg_N ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/ssax_A88195.d b/plugins/arm/v7/opdefs/ssax_A88195.d new file mode 100644 index 0000000..9339f41 --- /dev/null +++ b/plugins/arm/v7/opdefs/ssax_A88195.d @@ -0,0 +1,79 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title SSAX + +@id 194 + +@desc { + + Signed Subtract and Add with Exchange exchanges the two halfwords of the second operand, performs one 16-bit integer subtraction and one 16-bit addition, and writes the results to the destination register. It sets the APSR.GE bits according to the results. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 1 1 0 Rn(4) 1 1 1 1 Rd(4) 0 0 0 0 Rm(4) + + @syntax { + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm ssax ?reg_D reg_N reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 0 0 1 Rn(4) Rd(4) 1 1 1 1 0 1 0 1 Rm(4) + + @syntax { + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm ssax ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/ssub16_A88196.d b/plugins/arm/v7/opdefs/ssub16_A88196.d new file mode 100644 index 0000000..8b98339 --- /dev/null +++ b/plugins/arm/v7/opdefs/ssub16_A88196.d @@ -0,0 +1,79 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title SSUB16 + +@id 195 + +@desc { + + Signed Subtract 16 performs two 16-bit signed integer subtractions, and writes the results to the destination register. It sets the APSR.GE bits according to the results of the subtractions. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 1 0 1 Rn(4) 1 1 1 1 Rd(4) 0 0 0 0 Rm(4) + + @syntax { + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm ssub16 ?reg_D reg_N reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 0 0 1 Rn(4) Rd(4) 1 1 1 1 0 1 1 1 Rm(4) + + @syntax { + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm ssub16 ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/ssub8_A88197.d b/plugins/arm/v7/opdefs/ssub8_A88197.d new file mode 100644 index 0000000..d5a8c14 --- /dev/null +++ b/plugins/arm/v7/opdefs/ssub8_A88197.d @@ -0,0 +1,79 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title SSUB8 + +@id 196 + +@desc { + + Signed Subtract 8 performs four 8-bit signed integer subtractions, and writes the results to the destination register. It sets the APSR.GE bits according to the results of the subtractions. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 1 0 0 Rn(4) 1 1 1 1 Rd(4) 0 0 0 0 Rm(4) + + @syntax { + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm ssub8 ?reg_D reg_N reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 0 0 1 Rn(4) Rd(4) 1 1 1 1 1 1 1 1 Rm(4) + + @syntax { + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm ssub8 ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/sub_A88224.d b/plugins/arm/v7/opdefs/sub_A88224.d new file mode 100644 index 0000000..d1689bb --- /dev/null +++ b/plugins/arm/v7/opdefs/sub_A88224.d @@ -0,0 +1,97 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title SUB (register-shifted register) + +@id 223 + +@desc { + + This instruction subtracts a register-shifted register value from a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 0 0 1 0 S(1) Rn(4) Rd(4) Rs(4) 0 type(2) 1 Rm(4) + + @syntax { + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) + + } + + @asm sub ?reg_D reg_N reg_M shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) + + } + + @asm subs ?reg_D reg_N reg_M shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/sub_A88226.d b/plugins/arm/v7/opdefs/sub_A88226.d new file mode 100644 index 0000000..3c6e9fd --- /dev/null +++ b/plugins/arm/v7/opdefs/sub_A88226.d @@ -0,0 +1,141 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title SUB (SP minus register) + +@id 225 + +@desc { + + This instruction subtracts an optionally-shifted register value from the SP value, and writes the result to the destination register. + +} + +@encoding (T1) { + + @word 1 1 1 0 1 0 1 1 1 0 1 S(1) 1 1 0 1 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) + + @syntax { + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_SP = Register(13) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } + + @asm sub ?reg_D reg_SP reg_M ?shift + + } + + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_SP = Register(13) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } + + @asm subs ?reg_D reg_SP reg_M ?shift + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 0 0 1 0 S(1) 1 1 0 1 Rd(4) imm5(5) type(2) 0 Rm(4) + + @syntax { + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_SP = Register(13) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm sub ?reg_D reg_SP reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_SP = Register(13) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm subs ?reg_D reg_SP reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/sxtab16_A88231.d b/plugins/arm/v7/opdefs/sxtab16_A88231.d new file mode 100644 index 0000000..6a97ca6 --- /dev/null +++ b/plugins/arm/v7/opdefs/sxtab16_A88231.d @@ -0,0 +1,81 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title SXTAB16 + +@id 230 + +@desc { + + Signed Extend and Add Byte 16 extracts two 8-bit values from a register, sign-extends them to 16 bits each, adds the results to two 16-bit values from another register, and writes the final results to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit values. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 0 0 1 0 Rn(4) 1 1 1 1 Rd(4) 1 0 rotate(2) Rm(4) + + @syntax { + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') + + } + + @asm sxtab16 ?reg_D reg_N reg_M ?rotation + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 1 0 0 0 Rn(4) Rd(4) rotate(2) 0 0 0 1 1 1 Rm(4) + + @syntax { + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') + + } + + @asm sxtab16 ?reg_D reg_N reg_M ?rotation + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/sxtab_A88230.d b/plugins/arm/v7/opdefs/sxtab_A88230.d new file mode 100644 index 0000000..d40c0fd --- /dev/null +++ b/plugins/arm/v7/opdefs/sxtab_A88230.d @@ -0,0 +1,81 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title SXTAB + +@id 229 + +@desc { + + Signed Extend and Add Byte extracts an 8-bit value from a register, sign-extends it to 32 bits, adds the result to the value in another register, and writes the final result to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit value. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 0 1 0 0 Rn(4) 1 1 1 1 Rd(4) 1 0 rotate(2) Rm(4) + + @syntax { + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') + + } + + @asm sxtab ?reg_D reg_N reg_M ?rotation + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 1 0 1 0 Rn(4) Rd(4) rotate(2) 0 0 0 1 1 1 Rm(4) + + @syntax { + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') + + } + + @asm sxtab ?reg_D reg_N reg_M ?rotation + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/sxtah_A88232.d b/plugins/arm/v7/opdefs/sxtah_A88232.d new file mode 100644 index 0000000..ca6b69b --- /dev/null +++ b/plugins/arm/v7/opdefs/sxtah_A88232.d @@ -0,0 +1,81 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title SXTAH + +@id 231 + +@desc { + + Signed Extend and Add Halfword extracts a 16-bit value from a register, sign-extends it to 32 bits, adds the result to a value from another register, and writes the final result to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 16-bit value. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 0 0 0 0 Rn(4) 1 1 1 1 Rd(4) 1 0 rotate(2) Rm(4) + + @syntax { + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') + + } + + @asm sxtah ?reg_D reg_N reg_M ?rotation + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 1 0 1 1 Rn(4) Rd(4) rotate(2) 0 0 0 1 1 1 Rm(4) + + @syntax { + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') + + } + + @asm sxtah ?reg_D reg_N reg_M ?rotation + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/sxtb16_A88234.d b/plugins/arm/v7/opdefs/sxtb16_A88234.d new file mode 100644 index 0000000..1299a91 --- /dev/null +++ b/plugins/arm/v7/opdefs/sxtb16_A88234.d @@ -0,0 +1,79 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title SXTB16 + +@id 233 + +@desc { + + Signed Extend Byte 16 extracts two 8-bit values from a register, sign-extends them to 16 bits each, and writes the results to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit values. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 0 0 1 0 1 1 1 1 1 1 1 1 Rd(4) 1 0 rotate(2) Rm(4) + + @syntax { + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') + + } + + @asm sxtb16 ?reg_D reg_M ?rotation + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 1 0 0 0 1 1 1 1 Rd(4) rotate(2) 0 0 0 1 1 1 Rm(4) + + @syntax { + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') + + } + + @asm sxtb16 ?reg_D reg_M ?rotation + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/sxtb_A88233.d b/plugins/arm/v7/opdefs/sxtb_A88233.d new file mode 100644 index 0000000..d9c30e9 --- /dev/null +++ b/plugins/arm/v7/opdefs/sxtb_A88233.d @@ -0,0 +1,99 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title SXTB + +@id 232 + +@desc { + + Signed Extend Byte extracts an 8-bit value from a register, sign-extends it to 32 bits, and writes the result to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit value. + +} + +@encoding (t1) { + + @half 1 0 1 1 0 0 1 0 0 1 Rm(3) Rd(3) + + @syntax { + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + rotation = Rotation(0) + + } + + @asm sxtb ?reg_D reg_M ?rotation + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 0 1 0 0 1 0 0 1 1 1 1 1 1 1 1 Rd(4) 1 0 rotate(2) Rm(4) + + @syntax { + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') + + } + + @asm sxtb.w ?reg_D reg_M ?rotation + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 1 0 1 0 1 1 1 1 Rd(4) rotate(2) 0 0 0 1 1 1 Rm(4) + + @syntax { + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') + + } + + @asm sxtb ?reg_D reg_M ?rotation + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/sxth_A88235.d b/plugins/arm/v7/opdefs/sxth_A88235.d new file mode 100644 index 0000000..080d85c --- /dev/null +++ b/plugins/arm/v7/opdefs/sxth_A88235.d @@ -0,0 +1,99 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title SXTH + +@id 234 + +@desc { + + Signed Extend Halfword extracts a 16-bit value from a register, sign-extends it to 32 bits, and writes the result to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 16-bit value. + +} + +@encoding (t1) { + + @half 1 0 1 1 0 0 1 0 0 0 Rm(3) Rd(3) + + @syntax { + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + rotation = Rotation(0) + + } + + @asm sxth ?reg_D reg_M ?rotation + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 0 1 0 0 0 0 0 1 1 1 1 1 1 1 1 Rd(4) 1 0 rotate(2) Rm(4) + + @syntax { + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') + + } + + @asm sxth.w ?reg_D reg_M ?rotation + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 1 0 1 1 1 1 1 1 Rd(4) rotate(2) 0 0 0 1 1 1 Rm(4) + + @syntax { + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') + + } + + @asm sxth ?reg_D reg_M ?rotation + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/wfe_A88424.d b/plugins/arm/v7/opdefs/wfe_A88424.d new file mode 100644 index 0000000..84f2a9a --- /dev/null +++ b/plugins/arm/v7/opdefs/wfe_A88424.d @@ -0,0 +1,75 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title WFE + +@id 423 + +@desc { + + Wait For Event is a hint instruction that permits the processor to enter a low-power state until one of a number of events occurs, including events signaled by executing the SEV instruction on any processor in the multiprocessor system. For more information, see Wait For Event and Send Event on page B1-1199. In an implementation that includes the Virtualization Extensions, if HCR.TWE is set to 1, execution of a WFE instruction in a Non-secure mode other than Hyp mode generates a Hyp Trap exception if, ignoring the value of the HCR.TWE bit, conditions permit the processor to suspend execution. For more information see Trapping use of the WFI and WFE instructions on page B1-1255. + +} + +@encoding (t1) { + + @half 1 0 1 1 1 1 1 1 0 0 1 0 0 0 0 0 + + @syntax { + + @asm wfe + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 0 0 1 1 1 0 1 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 + + @syntax { + + @asm wfe.w + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 1 1 0 0 1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 + + @syntax { + + @asm wfe + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + |