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Diffstat (limited to 'src/arch/arm/v7/opdefs/and_A8815.d')
-rw-r--r-- | src/arch/arm/v7/opdefs/and_A8815.d | 52 |
1 files changed, 52 insertions, 0 deletions
diff --git a/src/arch/arm/v7/opdefs/and_A8815.d b/src/arch/arm/v7/opdefs/and_A8815.d new file mode 100644 index 0000000..5ace3fa --- /dev/null +++ b/src/arch/arm/v7/opdefs/and_A8815.d @@ -0,0 +1,52 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title AND (register-shifted register) + +@desc This instruction performs a bitwise AND of a register value and a register-shifted register value. It writes the result to the destination register, and can optionally update the condition flags based on the result. + +@encoding (A1) { + + @word cond(4) 0 0 0 0 0 0 0 S(1) Rn(4) Rd(4) Rs(4) 0 type(2) 1 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> <reg_shift> + + @conv { + + reg_shift = RegisterShift(type, Rs) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + setflags = (S == '1') + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) + + } + +} + |