diff options
Diffstat (limited to 'src/arch/arm/v7/opdefs/smlal_A88178.d')
-rw-r--r-- | src/arch/arm/v7/opdefs/smlal_A88178.d | 57 |
1 files changed, 26 insertions, 31 deletions
diff --git a/src/arch/arm/v7/opdefs/smlal_A88178.d b/src/arch/arm/v7/opdefs/smlal_A88178.d index a3a36aa..03da53c 100644 --- a/src/arch/arm/v7/opdefs/smlal_A88178.d +++ b/src/arch/arm/v7/opdefs/smlal_A88178.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2014 Cyrille Bagard + * Copyright (C) 2015 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,52 +23,47 @@ @title SMLAL -@encoding(T1) { +@desc Signed Multiply Accumulate Long multiplies two signed 32-bit values to produce a 64-bit value, and accumulates this with a 64-bit value. In ARM instructions, the condition flags can optionally be updated based on the result. Use of this option adversely affects performance on many processor implementations. - @word 1 1 1 1 1 0 1 1 1 1 0 0 Rn(4) RdLo(4) RdHi(4) 0 0 0 0 Rm(4) +@encoding (T1) { - @syntax <RdLo> <RdHi> <Rn> <Rm> + @word 1 1 1 1 1 0 1 1 1 1 0 0 Rn(4) RdLo(4) RdHi(4) 0 0 0 0 Rm(4) - @conv { + @syntax <reg_DLO> <reg_DHI> <reg_N> <reg_M> - RdLo = Register(RdLo) - RdHi = Register(RdHi) - Rn = Register(Rn) - Rm = Register(Rm) + @conv { - } + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) - @rules { - - //if dLo IN {13,15} || dHi IN {13,15} || n IN {13,15} || m IN {13,15} then UNPREDICTABLE; - //if dHi == dLo then UNPREDICTABLE; - - } + } } -@encoding(A1) { +@encoding (A1) { - @word cond(4) 0 0 0 0 1 1 1 S(1) RdHi(4) RdLo(4) Rm(4) 1 0 0 1 Rn(4) + @word cond(4) 0 0 0 0 1 1 1 S(1) RdHi(4) RdLo(4) Rm(4) 1 0 0 1 Rn(4) - @syntax {S} {c} <RdLo> <RdHi> <Rn> <Rm> + @syntax <reg_DLO> <reg_DHI> <reg_N> <reg_M> - @conv { + @conv { - S = SetFlags(S) - c = Condition(cond) - RdLo = Register(RdLo) - RdHi = Register(RdHi) - Rn = Register(Rn) - Rm = Register(Rm) + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + setflags = (S == '1') - } + } - @rules { + @rules { - //if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE; - //if dHi == dLo then UNPREDICTABLE; + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) - } + } } + |