diff options
Diffstat (limited to 'src/arch/arm/v7')
| -rw-r--r-- | src/arch/arm/v7/arm.c | 34 | ||||
| -rw-r--r-- | src/arch/arm/v7/thumb_32.c | 10 |
2 files changed, 16 insertions, 28 deletions
diff --git a/src/arch/arm/v7/arm.c b/src/arch/arm/v7/arm.c index b536770..542d521 100644 --- a/src/arch/arm/v7/arm.c +++ b/src/arch/arm/v7/arm.c @@ -30,6 +30,7 @@ #include "opcodes/arm_opcodes.h" #include "opcodes/opcodes_tmp_arm.h" +#include "../../undefined.h" #include "../../../common/bconst.h" @@ -2074,8 +2075,7 @@ static GArchInstruction *process_armv7_arm_coprocessor_instructions_and_supervis op = (raw >> 4) & 0x1; if ((op1 & b111110) == b000000) - /* UNDEFINED */ - assert(false); + result = g_undef_instruction_new(IBS_UNDEFINED); else if ((op1 & b110000) == b110000) result = armv7_read_arm_instr_svc_previously_swi(raw); @@ -2249,23 +2249,20 @@ static GArchInstruction *process_armv7_arm_memory_hints_advanced_simd_instructio assert(false); else if ((op1 & b1110111) == b1000001) - /* (treat as NOP */ - assert(false); + result = g_undef_instruction_new(IBS_NOP); else if ((op1 & b1110111) == b1000101) result = armv7_read_arm_instr_pli_immediate_literal(raw); else if ((op1 & b1110011) == b1000011) - /* UNPREDICTABLE */ - assert(false); + result = g_undef_instruction_new(IBS_UNPREDICTABLE); else if ((op1 & b1110111) == b1010101) { if (rn != b1111) result = armv7_read_arm_instr_pld_pldw_immediate(raw); else - /* UNPREDICTABLE */ - assert(false); + result = g_undef_instruction_new(IBS_UNPREDICTABLE); } @@ -2279,21 +2276,18 @@ static GArchInstruction *process_armv7_arm_memory_hints_advanced_simd_instructio } else if (op1 == b1010011) - /* UNPREDICTABLE */ - assert(false); + result = g_undef_instruction_new(IBS_UNPREDICTABLE); else if (op1 == b1010111) { if (op2 == b0000) - /* UNPREDICTABLE */ - assert(false); + result = g_undef_instruction_new(IBS_UNPREDICTABLE); else if (op2 == b0001) result = armv7_read_arm_instr_clrex(raw); else if ((op2 & b1110) == b0010) - /* UNPREDICTABLE */ - assert(false); + result = g_undef_instruction_new(IBS_UNPREDICTABLE); else if (op2 == b0100) result = armv7_read_arm_instr_dsb(raw); @@ -2305,22 +2299,18 @@ static GArchInstruction *process_armv7_arm_memory_hints_advanced_simd_instructio result = armv7_read_arm_instr_isb(raw); else if (op2 == b0111) - /* UNPREDICTABLE */ - assert(false); + result = g_undef_instruction_new(IBS_UNPREDICTABLE); else if ((op2 & b1000) == b1000) - /* UNPREDICTABLE */ - assert(false); + result = g_undef_instruction_new(IBS_UNPREDICTABLE); } else if ((op1 & b1111011) == b1011011) - /* UNPREDICTABLE */ - assert(false); + result = g_undef_instruction_new(IBS_UNPREDICTABLE); else if ((op1 & b1110111) == b1100001 && (op2 & b0001) == b0000) - /* (treat as NOP */ - assert(false); + result = g_undef_instruction_new(IBS_NOP); else if ((op1 & b1110111) == b1100101 && (op2 & b0001) == b0000) result = armv7_read_arm_instr_pli_register(raw); diff --git a/src/arch/arm/v7/thumb_32.c b/src/arch/arm/v7/thumb_32.c index c1e3f3c..9dbad13 100644 --- a/src/arch/arm/v7/thumb_32.c +++ b/src/arch/arm/v7/thumb_32.c @@ -30,6 +30,7 @@ #include "opcodes/thumb_32_opcodes.h" #include "opcodes/opcodes_tmp_thumb_32.h" +#include "../../undefined.h" #include "../../../common/bconst.h" @@ -177,10 +178,8 @@ GArchInstruction *process_armv7_thumb_32_instruction_set_encoding(uint32_t raw) else if ((op2 & b1100111) == b0000101) result = process_armv7_thumb_32_load_word(raw); - /* - else if ((op2 & b00xx111) == b00xx111) - undefined; - */ + else if ((op2 & b1100111) == b0000111) + result = g_undef_instruction_new(IBS_UNDEFINED); else if ((op2 & b1110001) == b0010000) /* Advanced SIMD element or structure load/store instructions on page A7-275 */ @@ -2213,8 +2212,7 @@ static GArchInstruction *process_armv7_thumb_32_coprocessor_advanced_simd_and_fl op = (raw >> 4) & 0x1; if ((op1 & b111110) == b000000) - /* UNDEFINED */ - assert(false); + result = g_undef_instruction_new(IBS_UNDEFINED); else if ((op1 & b110000) == b110000) /* Advanced SIMD data-processing instructions on page A7-261 */ |