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Diffstat (limited to 'src/arch/mips/opcodes.h')
-rw-r--r-- | src/arch/mips/opcodes.h | 107 |
1 files changed, 107 insertions, 0 deletions
diff --git a/src/arch/mips/opcodes.h b/src/arch/mips/opcodes.h new file mode 100644 index 0000000..276e752 --- /dev/null +++ b/src/arch/mips/opcodes.h @@ -0,0 +1,107 @@ + +/* OpenIDA - Outil d'analyse de fichiers binaires + * opcodes.h - prototypes pour la liste de tous les opcodes de l'architecture MIPS + * + * Copyright (C) 2009 Cyrille Bagard + * + * This file is part of OpenIDA. + * + * OpenIDA is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * OpenIDA is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +#ifndef _ARCH_MIPS_OPCODES_H +#define _ARCH_MIPS_OPCODES_H + + +#include "processor.h" +#include "instruction.h" + + + +/* Décode une instruction de type 'addiu rt, rs, imm'. */ +GArchInstruction *mips_read_instr_add_immediate_unsigned(const bin_t *, off_t *, off_t, vmpa_t, const GMipsProcessor *); + +/* Décode une instruction de type 'addu rd, rs, rt'. */ +GArchInstruction *mips_read_instr_add_unsigned(const bin_t *, off_t *, off_t, vmpa_t, const GMipsProcessor *); + + + +/* Décode une instruction de type 'and rd, rs, rt'. */ +GArchInstruction *mips_read_instr_and(const bin_t *, off_t *, off_t, vmpa_t, const GMipsProcessor *); + + + +/* Décode une instruction de type 'beq rs, rt, offset'. */ +GArchInstruction *mips_read_instr_branch_on_equal(const bin_t *, off_t *, off_t, vmpa_t, const GMipsProcessor *); + +/* Décode une instruction de type 'beql rs, rt, offset'. */ +GArchInstruction *mips_read_instr_branch_on_equal_likely(const bin_t *, off_t *, off_t, vmpa_t, const GMipsProcessor *); + +/* Décode une instruction de type 'bgezal rs, offset'. */ +GArchInstruction *mips_read_instr_branch_on_greater_than_or_equal_to_zero_and_link(const bin_t *, off_t *, off_t, vmpa_t, const GMipsProcessor *); + +/* Décode une instruction de type 'bne rs, rt, offset'. */ +GArchInstruction *mips_read_instr_branch_on_not_equal(const bin_t *, off_t *, off_t, vmpa_t, const GMipsProcessor *); + + + +/* Décode une instruction de type 'jr rs'. */ +GArchInstruction *mips_read_instr_jump_register(const bin_t *, off_t *, off_t, vmpa_t, const GMipsProcessor *); + +/* Décode une instruction de type 'jalr[.hb] [rd, ]rs'. */ +GArchInstruction *mips_read_instr_jump_and_link_register(const bin_t *, off_t *, off_t, vmpa_t, const GMipsProcessor *); + + + +/* Décode une instruction de type 'lbu rt, offset(rs)'. */ +GArchInstruction *mips_read_instr_load_byte_unisgned(const bin_t *, off_t *, off_t, vmpa_t, const GMipsProcessor *); + +/* Décode une instruction de type 'lui rt, imm'. */ +GArchInstruction *mips_read_instr_load_upper_immediate(const bin_t *, off_t *, off_t, vmpa_t, const GMipsProcessor *); + +/* Décode une instruction de type 'lw rt, offset(rs)'. */ +GArchInstruction *mips_read_instr_load_word(const bin_t *, off_t *, off_t, vmpa_t, const GMipsProcessor *); + + + +/* Décode une instruction de type 'nop'. */ +GArchInstruction *mips_read_instr_nop(const bin_t *, off_t *, off_t, vmpa_t, const GMipsProcessor *); + + + +/* Décode une instruction de type 'sra rd, rt, sa'. */ +GArchInstruction *mips_read_instr_shift_word_right_arithmetic(const bin_t *, off_t *, off_t, vmpa_t, const GMipsProcessor *); + + + +/* Décode une instruction de type 'sb rt, offset(rs)'. */ +GArchInstruction *mips_read_instr_store_byte(const bin_t *, off_t *, off_t, vmpa_t, const GMipsProcessor *); + +/* Décode une instruction de type 'sw rt, offset(rs)'. */ +GArchInstruction *mips_read_instr_store_word(const bin_t *, off_t *, off_t, vmpa_t, const GMipsProcessor *); + + + + +/* Décode une instruction de type 'subu rd, rs, rt'. */ +GArchInstruction *mips_read_instr_subtract_unsigned_word(const bin_t *, off_t *, off_t, vmpa_t, const GMipsProcessor *); + +/* Décode une instruction de type 'sub rd, rs, rt'. */ +GArchInstruction *mips_read_instr_subtract_word(const bin_t *, off_t *, off_t, vmpa_t, const GMipsProcessor *); + + + + +#endif /* _ARCH_MIPS_OPCODES_H */ |