6 files changed, 12 insertions, 12 deletions
diff --git a/src/arch/arm/v7/opdefs/add_A884.d b/src/arch/arm/v7/opdefs/add_A884.d
index 90e1235..fb79567 100644
--- a/src/arch/arm/v7/opdefs/add_A884.d
+++ b/src/arch/arm/v7/opdefs/add_A884.d
@@ -101,7 +101,7 @@
 
         Rd = Register(Rd)
         Rn = Register(Rn)
-        const = ZeroExtend((i:imm3:imm8, 12, 32)
+        const = ZeroExtend(i:imm3:imm8, 12, 32)
 
     }
 
diff --git a/src/arch/arm/v7/opdefs/add_A889.d b/src/arch/arm/v7/opdefs/add_A889.d
index 1f81776..3c9d432 100644
--- a/src/arch/arm/v7/opdefs/add_A889.d
+++ b/src/arch/arm/v7/opdefs/add_A889.d
@@ -101,7 +101,7 @@
 
         Rd = Register(Rd)
         SP = Register(13)
-        const = ZeroExtend((i:imm3:imm8, 12, 32)
+        const = ZeroExtend(i:imm3:imm8, 12, 32)
 
     }
 
diff --git a/src/arch/arm/v7/opdefs/b_A8818.d b/src/arch/arm/v7/opdefs/b_A8818.d
index f06367b..ab5971f 100644
--- a/src/arch/arm/v7/opdefs/b_A8818.d
+++ b/src/arch/arm/v7/opdefs/b_A8818.d
@@ -25,14 +25,14 @@
 
 @encoding(t1) {
 
-    @half 1 1 0 1 cond(4) top(1) imm8(7)
+    @half 1 1 0 1 cond(4) imm8(8)
 
     @syntax {c} <label>
 
     @conv {
 
         c = Condition(cond)
-        label = SignExtend(top:imm8:'0', top, 32)
+        label = SignExtend(imm8:'0', imm8 & 0x80, 32)
 
     }
 
@@ -56,13 +56,13 @@
 
 @encoding(t2) {
 
-    @half 1 1 1 0 0 top(1) imm11(10)
+    @half 1 1 1 0 0 imm11(11)
 
     @syntax <label>
 
     @conv {
 
-        label = SignExtend(top:imm11:'0', top, 32)
+        label = SignExtend(imm11:'0', imm11 & 0x400, 32)
 
     }
 
@@ -147,14 +147,14 @@
 
 @encoding(A1) {
 
-    @word cond(4) 1 0 1 0 top(1) imm24(23)
+    @word cond(4) 1 0 1 0 imm24(24)
 
     @syntax {c} <label>
 
     @conv {
 
         c = Condition(cond)
-        label = SignExtend(top:imm24:'00', top, 32)
+        label = SignExtend(imm24:'00', imm24 & 0x800000, 32)
 
     }
 
diff --git a/src/arch/arm/v7/opdefs/bl_A8825.d b/src/arch/arm/v7/opdefs/bl_A8825.d
index ce4870c..183ba36 100644
--- a/src/arch/arm/v7/opdefs/bl_A8825.d
+++ b/src/arch/arm/v7/opdefs/bl_A8825.d
@@ -91,7 +91,7 @@
 
     @conv {
 
-        imm32 = SignExtend(imm24:'00', 0, 32)
+        imm32 = SignExtend(imm24:'00', imm24 & 0x800000, 32)
 
     }
 
@@ -119,7 +119,7 @@
 
     @conv {
 
-        imm32 = SignExtend(imm24:H:'0', 0, 32)
+        imm32 = SignExtend(imm24:H:'0', imm24 & 0x800000, 32)
 
     }
 
diff --git a/src/arch/arm/v7/opdefs/sub_A88221.d b/src/arch/arm/v7/opdefs/sub_A88221.d
index 0ef0e11..ec6f241 100644
--- a/src/arch/arm/v7/opdefs/sub_A88221.d
+++ b/src/arch/arm/v7/opdefs/sub_A88221.d
@@ -101,7 +101,7 @@
 
         Rd = Register(Rd)
         Rn = Register(Rn)
-        const = ZeroExtend((i:imm3:imm8, 12, 32)
+        const = ZeroExtend(i:imm3:imm8, 12, 32)
 
     }
 
diff --git a/src/arch/arm/v7/opdefs/sub_A88225.d b/src/arch/arm/v7/opdefs/sub_A88225.d
index 9c29624..e37997f 100644
--- a/src/arch/arm/v7/opdefs/sub_A88225.d
+++ b/src/arch/arm/v7/opdefs/sub_A88225.d
@@ -79,7 +79,7 @@
 
         Rd = Register(Rd)
         SP = Register(13)
-        const = ZeroExtend((i:imm3:imm8, 12, 32)
+        const = ZeroExtend(i:imm3:imm8, 12, 32)
 
     }