index
:
chrysalide.git
gtk4
master
Chrysalide - Reverse Engineering Factory
Cyrille Bagard
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
plugins
/
arm
/
v7
Age
Commit message (
Collapse
)
Author
2021-01-09
Changed some installation paths and included a pkgconfig configuration.
Cyrille Bagard
2020-10-20
Fixed some compilation warnings.
Cyrille Bagard
2020-09-07
Rewritten some code managing comments.
Cyrille Bagard
2020-08-22
Defined paths to access to the instruction operands.
Cyrille Bagard
2020-07-27
Replaced all BLC_* constants by the new DLC_* values.
Cyrille Bagard
2020-06-21
Reorganized the code for target operands.
Cyrille Bagard
2020-05-21
Changed the hierarchy of format objects.
Cyrille Bagard
2020-04-21
Redefined the interface for creating new processors from Python.
Cyrille Bagard
2020-04-19
Changed the way the key for an architecture is provided.
Cyrille Bagard
2020-04-05
Removed some non-POSIX variable names in Makefiles.
Cyrille Bagard
2020-03-01
Given some priority to Elf PLT entries during the disassembly process.
Cyrille Bagard
2020-02-29
Broken ARMv7 basic blocks depending on conditional flags.
Cyrille Bagard
2020-02-18
Relocated the raw instructions.
Cyrille Bagard
2020-02-17
Relocated the undefined instructions.
Cyrille Bagard
2020-02-04
Updated copyright headers.
Cyrille Bagard
2020-01-30
Compressed some architecture instruction properties.
Cyrille Bagard
2020-01-15
Reorganized the architecture operands.
Cyrille Bagard
2019-09-12
Replaced some database item properties by new flags.
Cyrille Bagard
2019-09-08
Fixed the mask used for some ARMv7 SIMD instructions decoding.
Cyrille Bagard
2019-05-12
Simplified the way processors are registered.
Cyrille Bagard
2019-02-09
Fixed another batch of memory leaks.
Cyrille Bagard
2019-01-25
Fixed some Thumb decodings for ARMv7 branch instructions.
Cyrille Bagard
2019-01-08
Marked the ARMv7 branch instructions with the LR register as return points.
Cyrille Bagard
2018-11-27
Used the format endianness when fetching ARM ldr values.
Cyrille Bagard
2018-10-30
Defined the parent directory as the working location for generation.
Cyrille Bagard
2018-10-30
Untabified code.
Cyrille Bagard
2018-10-14
Typo.
Cyrille Bagard
2018-08-29
Fixed the dist rule in Makefiles.
Cyrille Bagard
2018-08-11
Added a basic check before releasing cached registers.
Cyrille Bagard
2018-07-19
Deleted all references to any asm syntax.
Cyrille Bagard
2018-06-19
Updated Makefiles to create only one _PyGObject_API structure.
Cyrille Bagard
2018-06-19
Avoided to cache ARMv7 instruction keyword when unneeded.
Cyrille Bagard
2018-06-19
Built ARMv7 dynamic vector tables with the right number of registers.
Cyrille Bagard
2018-06-19
Fixed conditions for some ARMv7 SIMD instruction syntaxes.
Cyrille Bagard
2018-06-18
Fixed various bugs in ARMv7 operand decoding helpers.
Cyrille Bagard
2018-06-06
Hidden virtual addresses when code runs in a VM.
Cyrille Bagard
2018-06-05
Released the mutex even in case of register loading failure.
Cyrille Bagard
2018-06-01
Added a missing directory to SUBDIRS.
Cyrille Bagard
2018-05-31
Handled lists of simples ARMv7 SIMD registers.
Cyrille Bagard
2018-05-30
Supported a few extra ARMv7 SIMD instructions.
Cyrille Bagard
2018-05-29
Updated the ARMv7 SIMD decoding process.
Cyrille Bagard
2018-05-29
Added support for the last remaining ARMv7 basic instructions.
Cyrille Bagard
2018-05-29
Fixed function names for some Thumb32 decoding calls.
Cyrille Bagard
2018-05-28
Added support for some ARMv7 SIMD instructions.
Cyrille Bagard
2018-05-28
Included support for ARMv7 system instructions.
Cyrille Bagard
2018-05-28
Relied on register objects as often as possible.
Cyrille Bagard
2018-05-28
Registered a missing ARMv7 type.
Cyrille Bagard
2018-05-19
Stopped trying to resolve loaded values by all means.
Cyrille Bagard
2018-05-19
Called the FP and IP ARMv7 registers by their name.
Cyrille Bagard
2018-05-19
Fixed the loading of ARMv7 written-back registers.
Cyrille Bagard
[next]