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AgeCommit message (Collapse)Author
2021-12-26Provide a method to hash all ARMv7 operands.Cyrille Bagard
2021-09-26Provide a serialization capability for operands.Cyrille Bagard
2021-08-24Serialize registers when needed.Cyrille Bagard
2021-08-21Define all architecture instructions as serializable.Cyrille Bagard
2021-06-01Improve the code quality by renaming the type for packed buffers.Cyrille Bagard
2021-01-09Changed some installation paths and included a pkgconfig configuration.Cyrille Bagard
2020-10-20Fixed some compilation warnings.Cyrille Bagard
2020-09-07Rewritten some code managing comments.Cyrille Bagard
2020-08-22Defined paths to access to the instruction operands.Cyrille Bagard
2020-07-27Replaced all BLC_* constants by the new DLC_* values.Cyrille Bagard
2020-06-21Reorganized the code for target operands.Cyrille Bagard
2020-05-21Changed the hierarchy of format objects.Cyrille Bagard
2020-04-21Redefined the interface for creating new processors from Python.Cyrille Bagard
2020-04-19Changed the way the key for an architecture is provided.Cyrille Bagard
2020-04-05Removed some non-POSIX variable names in Makefiles.Cyrille Bagard
2020-03-01Given some priority to Elf PLT entries during the disassembly process.Cyrille Bagard
2020-02-29Broken ARMv7 basic blocks depending on conditional flags.Cyrille Bagard
2020-02-18Relocated the raw instructions.Cyrille Bagard
2020-02-17Relocated the undefined instructions.Cyrille Bagard
2020-02-04Updated copyright headers.Cyrille Bagard
2020-01-30Compressed some architecture instruction properties.Cyrille Bagard
2020-01-15Reorganized the architecture operands.Cyrille Bagard
2019-09-12Replaced some database item properties by new flags.Cyrille Bagard
2019-09-08Fixed the mask used for some ARMv7 SIMD instructions decoding.Cyrille Bagard
2019-05-12Simplified the way processors are registered.Cyrille Bagard
2019-02-09Fixed another batch of memory leaks.Cyrille Bagard
2019-01-25Fixed some Thumb decodings for ARMv7 branch instructions.Cyrille Bagard
2019-01-08Marked the ARMv7 branch instructions with the LR register as return points.Cyrille Bagard
2018-11-27Used the format endianness when fetching ARM ldr values.Cyrille Bagard
2018-10-30Defined the parent directory as the working location for generation.Cyrille Bagard
2018-10-30Untabified code.Cyrille Bagard
2018-10-14Typo.Cyrille Bagard
2018-08-29Fixed the dist rule in Makefiles.Cyrille Bagard
2018-08-11Added a basic check before releasing cached registers.Cyrille Bagard
2018-07-19Deleted all references to any asm syntax.Cyrille Bagard
2018-06-19Updated Makefiles to create only one _PyGObject_API structure.Cyrille Bagard
2018-06-19Avoided to cache ARMv7 instruction keyword when unneeded.Cyrille Bagard
2018-06-19Built ARMv7 dynamic vector tables with the right number of registers.Cyrille Bagard
2018-06-19Fixed conditions for some ARMv7 SIMD instruction syntaxes.Cyrille Bagard
2018-06-18Fixed various bugs in ARMv7 operand decoding helpers.Cyrille Bagard
2018-06-06Hidden virtual addresses when code runs in a VM.Cyrille Bagard
2018-06-05Released the mutex even in case of register loading failure.Cyrille Bagard
2018-06-01Added a missing directory to SUBDIRS.Cyrille Bagard
2018-05-31Handled lists of simples ARMv7 SIMD registers.Cyrille Bagard
2018-05-30Supported a few extra ARMv7 SIMD instructions.Cyrille Bagard
2018-05-29Updated the ARMv7 SIMD decoding process.Cyrille Bagard
2018-05-29Added support for the last remaining ARMv7 basic instructions.Cyrille Bagard
2018-05-29Fixed function names for some Thumb32 decoding calls.Cyrille Bagard
2018-05-28Added support for some ARMv7 SIMD instructions.Cyrille Bagard
2018-05-28Included support for ARMv7 system instructions.Cyrille Bagard
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