1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
|
/* Chrysalide - Outil d'analyse de fichiers binaires
* ##FILE## - traduction d'instructions ARMv7
*
* Copyright (C) 2017 Cyrille Bagard
*
* This file is part of Chrysalide.
*
* Chrysalide is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 3 of the License, or
* (at your option) any later version.
*
* Chrysalide is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Chrysalide. If not, see <http://www.gnu.org/licenses/>.
*/
@title VEXT
@id 308
@desc {
Vector Extract extracts elements from the bottom end of the second operand vector and the top end of the first, concatenates them and places the result in the destination vector. See Figure A8-1 for an example. The elements of the vectors are treated as being 8-bit fields. There is no distinction between data types. 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Vm Vn Vd Figure A8-1 VEXT doubleword operation for imm = 3 Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. Summary of access controls for Advanced SIMD functionality on page B1-1232 summarizes these controls. ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available as a VFP instruction encoding, see Conditional execution on page A8-288.
}
@encoding (T1) {
@word 1 1 1 0 1 1 1 1 1 D(1) 1 1 Vn(4) Vd(4) imm4(4) N(1) Q(1) M(1) 0 Vm(4)
@syntax {
@subid 1297
@assert {
Q == 1
}
@conv {
qwvec_D = QuadWordVector(D:Vd)
qwvec_N = QuadWordVector(N:Vn)
qwvec_M = QuadWordVector(M:Vm)
imm = Multiplication(8, imm4)
}
@asm vext.8 ?qwvec_D qwvec_N qwvec_M imm
}
@syntax {
@subid 1298
@assert {
Q == 0
}
@conv {
dwvec_D = DoubleWordVector(D:Vd)
dwvec_N = DoubleWordVector(N:Vn)
dwvec_M = DoubleWordVector(M:Vm)
imm = Multiplication(8, imm4)
}
@asm vext.8 ?dwvec_D dwvec_N dwvec_M imm
}
}
@encoding (A1) {
@word 1 1 1 0 1 1 1 1 1 D(1) 1 1 Vn(4) Vd(4) imm4(4) N(1) Q(1) M(1) 0 Vm(4)
@syntax {
@subid 1299
@assert {
Q == 1
}
@conv {
qwvec_D = QuadWordVector(D:Vd)
qwvec_N = QuadWordVector(N:Vn)
qwvec_M = QuadWordVector(M:Vm)
imm = Multiplication(8, imm4)
}
@asm vext.8 ?qwvec_D qwvec_N qwvec_M imm
}
@syntax {
@subid 1300
@assert {
Q == 0
}
@conv {
dwvec_D = DoubleWordVector(D:Vd)
dwvec_N = DoubleWordVector(N:Vn)
dwvec_M = DoubleWordVector(M:Vm)
imm = Multiplication(8, imm4)
}
@asm vext.8 ?dwvec_D dwvec_N dwvec_M imm
}
}
|
