1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
|
/* Chrysalide - Outil d'analyse de fichiers binaires
* ##FILE## - traduction d'instructions ARMv7
*
* Copyright (C) 2017 Cyrille Bagard
*
* This file is part of Chrysalide.
*
* Chrysalide is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 3 of the License, or
* (at your option) any later version.
*
* Chrysalide is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Chrysalide. If not, see <http://www.gnu.org/licenses/>.
*/
@title VRECPE
@id 358
@desc {
Vector Reciprocal Estimate finds an approximate reciprocal of each element in the operand vector, and places the results in the destination vector. The operand and result elements are the same type, and can be 32-bit floating-point numbers, or 32-bit unsigned integers. For details of the operation performed by this instruction see Floating-point reciprocal estimate and step on page A2-85. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. Summary of access controls for Advanced SIMD functionality on page B1-1232 summarizes these controls. ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available as a VFP instruction encoding, see Conditional execution on page A8-288.
}
@encoding (T1) {
@word 1 1 1 1 1 1 1 1 1 D(1) 1 1 size(2) 1 1 Vd(4) 0 1 0 F(1) 0 Q(1) M(1) 0 Vm(4)
@syntax {
@subid 2875
@assert {
Q == 1
F == 0
size == 10
}
@conv {
qwvec_D = QuadWordVector(D:Vd)
qwvec_M = QuadWordVector(M:Vm)
}
@asm vrecpe.u32 qwvec_D qwvec_M
}
@syntax {
@subid 2876
@assert {
Q == 1
F == 1
size == 10
}
@conv {
qwvec_D = QuadWordVector(D:Vd)
qwvec_M = QuadWordVector(M:Vm)
}
@asm vrecpe.f32 qwvec_D qwvec_M
}
@syntax {
@subid 2877
@assert {
Q == 0
F == 0
size == 10
}
@conv {
dwvec_D = DoubleWordVector(D:Vd)
dwvec_M = DoubleWordVector(M:Vm)
}
@asm vrecpe.u32 dwvec_D dwvec_M
}
@syntax {
@subid 2878
@assert {
Q == 0
F == 1
size == 10
}
@conv {
dwvec_D = DoubleWordVector(D:Vd)
dwvec_M = DoubleWordVector(M:Vm)
}
@asm vrecpe.f32 dwvec_D dwvec_M
}
}
@encoding (A1) {
@word 1 1 1 1 1 1 1 1 1 D(1) 1 1 size(2) 1 1 Vd(4) 0 1 0 F(1) 0 Q(1) M(1) 0 Vm(4)
@syntax {
@subid 2879
@assert {
Q == 1
F == 0
size == 10
}
@conv {
qwvec_D = QuadWordVector(D:Vd)
qwvec_M = QuadWordVector(M:Vm)
}
@asm vrecpe.u32 qwvec_D qwvec_M
}
@syntax {
@subid 2880
@assert {
Q == 1
F == 1
size == 10
}
@conv {
qwvec_D = QuadWordVector(D:Vd)
qwvec_M = QuadWordVector(M:Vm)
}
@asm vrecpe.f32 qwvec_D qwvec_M
}
@syntax {
@subid 2881
@assert {
Q == 0
F == 0
size == 10
}
@conv {
dwvec_D = DoubleWordVector(D:Vd)
dwvec_M = DoubleWordVector(M:Vm)
}
@asm vrecpe.u32 dwvec_D dwvec_M
}
@syntax {
@subid 2882
@assert {
Q == 0
F == 1
size == 10
}
@conv {
dwvec_D = DoubleWordVector(D:Vd)
dwvec_M = DoubleWordVector(M:Vm)
}
@asm vrecpe.f32 dwvec_D dwvec_M
}
}
|
