blob: 16b59dc8db63ab58beb41458ffb552bbd5887215 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
|
/* Chrysalide - Outil d'analyse de fichiers binaires
* ##FILE## - traduction d'instructions ARMv7
*
* Copyright (C) 2017 Cyrille Bagard
*
* This file is part of Chrysalide.
*
* Chrysalide is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 3 of the License, or
* (at your option) any later version.
*
* Chrysalide is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Chrysalide. If not, see <http://www.gnu.org/licenses/>.
*/
@title LDREXD
@id 76
@desc {
Load Register Exclusive Doubleword derives an address from a base register value, loads a 64-bit doubleword from memory, writes it to two registers and: • if the address has the Shared Memory attribute, marks the physical address as exclusive access for the executing processor in a global monitor • causes the executing processor to indicate an active exclusive access in the local monitor. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294.
}
@encoding (T1) {
@word 1 1 1 0 1 0 0 0 1 1 0 1 Rn(4) Rt(4) Rt2(4) 0 1 1 1 1 1 1 1
@syntax {
@subid 188
@conv {
reg_T = Register(Rt)
reg_T2 = Register(Rt2)
reg_N = Register(Rn)
maccess = MemAccessOffset(reg_N, NULL)
}
@asm ldrexd reg_T reg_T2 maccess
}
}
@encoding (A1) {
@word cond(4) 0 0 0 1 1 0 1 1 Rn(4) Rt(4) 1 1 1 1 1 0 0 1 1 1 1 1
@syntax {
@subid 189
@conv {
reg_T = Register(Rt)
reg_T2 = NextRegister(Rt)
reg_N = Register(Rn)
maccess = MemAccessOffset(reg_N, NULL)
}
@asm ldrexd reg_T reg_T2 maccess
@rules {
check g_arm_instruction_set_cond(cond)
}
}
}
|
