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| author | Cyrille Bagard <nocbos@gmail.com> | 2018-05-31 16:24:27 (GMT) |
|---|---|---|
| committer | Cyrille Bagard <nocbos@gmail.com> | 2018-05-31 16:24:27 (GMT) |
| commit | 48b4166d1f2931fa7f311b6ec1c77153052e63a0 (patch) | |
| tree | ae00744c32653ac8196b51f7060d00283071cf4f /plugins/arm/v7/helpers.h | |
| parent | c492a5c94cc20210bce8069db7235cbb7dd691e9 (diff) | |
Handled lists of simples ARMv7 SIMD registers.
Diffstat (limited to 'plugins/arm/v7/helpers.h')
| -rw-r--r-- | plugins/arm/v7/helpers.h | 81 |
1 files changed, 80 insertions, 1 deletions
diff --git a/plugins/arm/v7/helpers.h b/plugins/arm/v7/helpers.h index bf4bc5a..29ba021 100644 --- a/plugins/arm/v7/helpers.h +++ b/plugins/arm/v7/helpers.h @@ -64,6 +64,20 @@ }) +#define AlignedRegister(reg, align) \ + ({ \ + GArchOperand *__result; \ + GArmV7RegisterOperand *__cast; \ + __result = reg; \ + if (__result != NULL && align != 0) \ + { \ + __cast = G_ARMV7_REGISTER_OPERAND(__result); \ + g_armv7_register_operand_define_alignement(__cast, align); \ + } \ + __result; \ + }) + + #define ARMExpandImm(imm12) \ ({ \ GArchOperand *__result; \ @@ -197,6 +211,22 @@ }) +#define DynamicVectorTable(target, count, first, inc) \ + ({ \ + GArchOperand *__result; \ + size_t __i; \ + GArchRegister *__reg; \ + __result = g_armv7_reglist_operand_new(0); \ + for (__i = 0; __i < count; __i += inc) \ + { \ + __reg = g_armv7_simd_register_new(target, first + __i); \ + g_armv7_reglist_add_register(G_ARMV7_REGLIST_OPERAND(__result), \ + G_ARMV7_REGISTER(__reg)); \ + } \ + __result; \ + }) + + #define Endian(big) \ ({ \ GArchOperand *__result; \ @@ -296,6 +326,22 @@ __result; \ }) + +#define NextDoubleWordVector(ref, n) \ + ({ \ + GArchOperand *__result; \ + uint8_t __idx; \ + GArchRegister *__reg; \ + __idx = g_arm_register_get_index(G_ARM_REGISTER(ref)); \ + __reg = g_armv7_simd_register_new(SRM_DOUBLE_WORD, __idx + n); \ + if (__reg == NULL) \ + __result = NULL; \ + else \ + __result = g_armv7_register_operand_new(G_ARMV7_REGISTER(__reg)); \ + __result; \ + }) + + #define NextRegister(idx) \ ({ \ GArchOperand *__result; \ @@ -309,7 +355,7 @@ }) -#define NexSingleWordVector(prev) \ +#define NextSingleWordVector(prev) \ ({ \ GArchOperand *__result; \ uint8_t __idx; \ @@ -591,6 +637,39 @@ }) +#define VectorTable(list, count) \ + ({ \ + GArchOperand *__result; \ + size_t __i; \ + GArchRegister *__reg; \ + __result = g_armv7_reglist_operand_new(0); \ + for (__i = 0; __i < count; __i++) \ + { \ + __reg = g_register_operand_get_register(G_REGISTER_OPERAND(list[__i])); \ + g_object_unref(G_OBJECT(list[__i])); \ + g_armv7_reglist_add_register(G_ARMV7_REGLIST_OPERAND(__result), \ + G_ARMV7_REGISTER(__reg)); \ + } \ + __result; \ + }) + + +#define VectorTableDim1(op1) \ + VectorTable(((GArchOperand *[]) { op1 }), 1) + + +#define VectorTableDim2(op1, op2) \ + VectorTable(((GArchOperand *[]) { op1, op2 }), 2) + + +#define VectorTableDim3(op1, op2, op3) \ + VectorTable(((GArchOperand *[]) { op1, op2, op3 }), 3) + + +#define VectorTableDim4(op1, op2, op3, op4) \ + VectorTable(((GArchOperand *[]) { op1, op2, op3, op4 }), 4) + + #define WrittenBackReg(regop, writeback) \ ({ \ GArchOperand *__result; \ |