diff options
| author | Cyrille Bagard <nocbos@gmail.com> | 2018-05-31 16:24:27 (GMT) |
|---|---|---|
| committer | Cyrille Bagard <nocbos@gmail.com> | 2018-05-31 16:24:27 (GMT) |
| commit | 48b4166d1f2931fa7f311b6ec1c77153052e63a0 (patch) | |
| tree | ae00744c32653ac8196b51f7060d00283071cf4f /plugins/arm/v7/opdefs/A88344_vmov.d | |
| parent | c492a5c94cc20210bce8069db7235cbb7dd691e9 (diff) | |
Handled lists of simples ARMv7 SIMD registers.
Diffstat (limited to 'plugins/arm/v7/opdefs/A88344_vmov.d')
| -rw-r--r-- | plugins/arm/v7/opdefs/A88344_vmov.d | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/plugins/arm/v7/opdefs/A88344_vmov.d b/plugins/arm/v7/opdefs/A88344_vmov.d index a3de0b8..e653720 100644 --- a/plugins/arm/v7/opdefs/A88344_vmov.d +++ b/plugins/arm/v7/opdefs/A88344_vmov.d @@ -23,7 +23,7 @@ @title VMOV (between two ARM core registers and two single-precision registers) -@id 317 +@id 326 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 1497 + @subid 2381 @assert { @@ -48,7 +48,7 @@ @conv { swvec_M = SingleWordVector(Vm:M) - reg_Sm1 = NexSingleWordVector(swvec_M) + reg_Sm1 = NextSingleWordVector(swvec_M) reg_T = Register(Rt) reg_T2 = Register(Rt2) @@ -60,7 +60,7 @@ @syntax { - @subid 1498 + @subid 2382 @assert { @@ -73,7 +73,7 @@ reg_T = Register(Rt) reg_T2 = Register(Rt2) swvec_M = SingleWordVector(Vm:M) - reg_Sm1 = NexSingleWordVector(swvec_M) + reg_Sm1 = NextSingleWordVector(swvec_M) } @@ -89,7 +89,7 @@ @syntax { - @subid 1499 + @subid 2383 @assert { @@ -100,7 +100,7 @@ @conv { swvec_M = SingleWordVector(Vm:M) - reg_Sm1 = NexSingleWordVector(swvec_M) + reg_Sm1 = NextSingleWordVector(swvec_M) reg_T = Register(Rt) reg_T2 = Register(Rt2) @@ -112,7 +112,7 @@ @syntax { - @subid 1500 + @subid 2384 @assert { @@ -125,7 +125,7 @@ reg_T = Register(Rt) reg_T2 = Register(Rt2) swvec_M = SingleWordVector(Vm:M) - reg_Sm1 = NexSingleWordVector(swvec_M) + reg_Sm1 = NextSingleWordVector(swvec_M) } |