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authorCyrille Bagard <nocbos@gmail.com>2018-04-02 11:58:42 (GMT)
committerCyrille Bagard <nocbos@gmail.com>2018-04-02 12:39:30 (GMT)
commit1db4ef323b7a76093356ae76268132f3760e1631 (patch)
treefec36ee0ec1b6b2010b62ca4177edca0e31e2114 /plugins/arm/v7/opdefs/adc_A883.d
parent1bc80837dde03a32b5ab185067f7bd4c499a9850 (diff)
Rewritten the whole instruction definition format.
Diffstat (limited to 'plugins/arm/v7/opdefs/adc_A883.d')
-rw-r--r--plugins/arm/v7/opdefs/adc_A883.d69
1 files changed, 57 insertions, 12 deletions
diff --git a/plugins/arm/v7/opdefs/adc_A883.d b/plugins/arm/v7/opdefs/adc_A883.d
index a9c56d8..6371445 100644
--- a/plugins/arm/v7/opdefs/adc_A883.d
+++ b/plugins/arm/v7/opdefs/adc_A883.d
@@ -2,7 +2,7 @@
/* Chrysalide - Outil d'analyse de fichiers binaires
* ##FILE## - traduction d'instructions ARMv7
*
- * Copyright (C) 2015 Cyrille Bagard
+ * Copyright (C) 2017 Cyrille Bagard
*
* This file is part of Chrysalide.
*
@@ -23,28 +23,73 @@
@title ADC (register-shifted register)
-@desc Add with Carry (register-shifted register) adds a register value, the Carry flag value, and a register-shifted register value. It writes the result to the destination register, and can optionally update the condition flags based on the result.
+@id 2
+
+@desc {
+
+ Add with Carry (register-shifted register) adds a register value, the Carry flag value, and a register-shifted register value. It writes the result to the destination register, and can optionally update the condition flags based on the result.
+
+}
@encoding (A1) {
@word cond(4) 0 0 0 0 1 0 1 S(1) Rn(4) Rd(4) Rs(4) 0 type(2) 1 Rm(4)
- @syntax <reg_D> <reg_N> <reg_M> <reg_shift>
+ @syntax {
+
+ @assert {
+
+ S == 0
+
+ }
+
+ @conv {
+
+ reg_D = Register(Rd)
+ reg_N = Register(Rn)
+ reg_M = Register(Rm)
+ shift_t = UInt(type)
+ reg_S = Register(Rs)
+ shift = BuildRegShift(shift_t, reg_S)
+
+ }
+
+ @asm adc ?reg_D reg_N reg_M shift
- @conv {
+ @rules {
- reg_shift = RegisterShift(type, Rs)
- reg_D = Register(Rd)
- reg_N = Register(Rn)
- reg_M = Register(Rm)
- setflags = (S == '1')
+ check g_arm_instruction_set_cond(cond)
+
+ }
}
- @rules {
+ @syntax {
+
+ @assert {
+
+ S == 1
+
+ }
+
+ @conv {
+
+ reg_D = Register(Rd)
+ reg_N = Register(Rn)
+ reg_M = Register(Rm)
+ shift_t = UInt(type)
+ reg_S = Register(Rs)
+ shift = BuildRegShift(shift_t, reg_S)
+
+ }
+
+ @asm adcs ?reg_D reg_N reg_M shift
+
+ @rules {
+
+ check g_arm_instruction_set_cond(cond)
- if (setflags); chk_call ExtendKeyword("s")
- chk_call StoreCondition(cond)
+ }
}