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authorCyrille Bagard <nocbos@gmail.com>2018-04-02 11:58:42 (GMT)
committerCyrille Bagard <nocbos@gmail.com>2018-04-02 12:39:30 (GMT)
commit1db4ef323b7a76093356ae76268132f3760e1631 (patch)
treefec36ee0ec1b6b2010b62ca4177edca0e31e2114 /plugins/arm/v7/opdefs/ldr_A8865.d
parent1bc80837dde03a32b5ab185067f7bd4c499a9850 (diff)
Rewritten the whole instruction definition format.
Diffstat (limited to 'plugins/arm/v7/opdefs/ldr_A8865.d')
-rw-r--r--plugins/arm/v7/opdefs/ldr_A8865.d44
1 files changed, 29 insertions, 15 deletions
diff --git a/plugins/arm/v7/opdefs/ldr_A8865.d b/plugins/arm/v7/opdefs/ldr_A8865.d
index ebb4e09..e94eccb 100644
--- a/plugins/arm/v7/opdefs/ldr_A8865.d
+++ b/plugins/arm/v7/opdefs/ldr_A8865.d
@@ -2,7 +2,7 @@
/* Chrysalide - Outil d'analyse de fichiers binaires
* ##FILE## - traduction d'instructions ARMv7
*
- * Copyright (C) 2015 Cyrille Bagard
+ * Copyright (C) 2017 Cyrille Bagard
*
* This file is part of Chrysalide.
*
@@ -23,20 +23,30 @@
@title LDR (register, Thumb)
-@desc Load Register (register) calculates an address from a base register value and an offset register value, loads a word from memory, and writes it to a register. The offset register value can optionally be shifted. For information about memory accesses, see Memory accesses on page A8-294. The Thumb form of LDR (register) does not support register writeback.
+@id 64
+
+@desc {
+
+ Load Register (register) calculates an address from a base register value and an offset register value, loads a word from memory, and writes it to a register. The offset register value can optionally be shifted. For information about memory accesses, see Memory accesses on page A8-294. The Thumb form of LDR (register) does not support register writeback.
+
+}
@encoding (t1) {
@half 0 1 0 1 1 0 0 Rm(3) Rn(3) Rt(3)
- @syntax <reg_T> <mem_access>
+ @syntax {
- @conv {
+ @conv {
- reg_T = Register(Rt)
- reg_N = Register(Rn)
- reg_M = Register(Rm)
- mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, true, false, false)
+ reg_T = Register(Rt)
+ reg_N = Register(Rn)
+ reg_M = Register(Rm)
+ maccess = MemAccessOffset(reg_N, reg_M)
+
+ }
+
+ @asm ldr reg_T maccess
}
@@ -46,15 +56,19 @@
@word 1 1 1 1 1 0 0 0 0 1 0 1 Rn(4) Rt(4) 0 0 0 0 0 0 imm2(2) Rm(4)
- @syntax ".W" <reg_T> <mem_access>
+ @syntax {
+
+ @conv {
+
+ reg_T = Register(Rt)
+ reg_N = Register(Rn)
+ reg_M = Register(Rm)
+ shift = FixedShift(SRType_LSL, imm2)
+ maccess = MemAccessOffsetExtended(reg_N, reg_M, shift)
- @conv {
+ }
- reg_T = Register(Rt)
- reg_N = Register(Rn)
- reg_M = Register(Rm)
- shift = DecodeImmShift(0, imm2)
- mem_access = MakeMemoryAccess(reg_N, reg_M, shift, true, false, false)
+ @asm ldr.w reg_T maccess
}