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authorCyrille Bagard <nocbos@gmail.com>2018-04-02 11:58:42 (GMT)
committerCyrille Bagard <nocbos@gmail.com>2018-04-02 12:39:30 (GMT)
commit1db4ef323b7a76093356ae76268132f3760e1631 (patch)
treefec36ee0ec1b6b2010b62ca4177edca0e31e2114 /plugins/arm/v7/opdefs/mov_A88103.d
parent1bc80837dde03a32b5ab185067f7bd4c499a9850 (diff)
Rewritten the whole instruction definition format.
Diffstat (limited to 'plugins/arm/v7/opdefs/mov_A88103.d')
-rw-r--r--plugins/arm/v7/opdefs/mov_A88103.d71
1 files changed, 53 insertions, 18 deletions
diff --git a/plugins/arm/v7/opdefs/mov_A88103.d b/plugins/arm/v7/opdefs/mov_A88103.d
index cd3d75a..8a25367 100644
--- a/plugins/arm/v7/opdefs/mov_A88103.d
+++ b/plugins/arm/v7/opdefs/mov_A88103.d
@@ -2,7 +2,7 @@
/* Chrysalide - Outil d'analyse de fichiers binaires
* ##FILE## - traduction d'instructions ARMv7
*
- * Copyright (C) 2015 Cyrille Bagard
+ * Copyright (C) 2017 Cyrille Bagard
*
* This file is part of Chrysalide.
*
@@ -23,18 +23,28 @@
@title MOV (register, Thumb)
-@desc Move (register) copies a value from a register to the destination register. It can optionally update the condition flags based on the value.
+@id 102
+
+@desc {
+
+ Move (register) copies a value from a register to the destination register. It can optionally update the condition flags based on the value.
+
+}
@encoding (t1) {
@half 0 1 0 0 0 1 1 0 D(1) Rm(4) Rd(3)
- @syntax <reg_D> <reg_M>
+ @syntax {
+
+ @conv {
- @conv {
+ reg_D = Register(D:Rd)
+ reg_M = Register(Rm)
- reg_D = Register(D:Rd)
- reg_M = Register(Rm)
+ }
+
+ @asm mov reg_D reg_M
}
@@ -44,12 +54,16 @@
@half 0 0 0 0 0 0 0 0 0 0 Rm(3) Rd(3)
- @syntax "movs" <reg_D> <reg_M>
+ @syntax {
+
+ @conv {
+
+ reg_D = Register(Rd)
+ reg_M = Register(Rm)
- @conv {
+ }
- reg_D = Register(Rd)
- reg_M = Register(Rm)
+ @asm movs reg_D reg_M
}
@@ -59,20 +73,41 @@
@word 1 1 1 0 1 0 1 0 0 1 0 S(1) 1 1 1 1 0 0 0 0 Rd(4) 0 0 0 0 Rm(4)
- @syntax <reg_D> <reg_M>
+ @syntax {
+
+ @assert {
+
+ S == 0
- @conv {
+ }
- reg_D = Register(Rd)
- reg_M = Register(Rm)
- setflags = (S == '1')
+ @conv {
+
+ reg_D = Register(Rd)
+ reg_M = Register(Rm)
+
+ }
+
+ @asm mov.w reg_D reg_M
}
- @rules {
+ @syntax {
+
+ @assert {
+
+ S == 1
+
+ }
+
+ @conv {
+
+ reg_D = Register(Rd)
+ reg_M = Register(Rm)
+
+ }
- if (setflags); chk_call ExtendKeyword("s")
- chk_call ExtendKeyword(".w")
+ @asm movs.w reg_D reg_M
}