Rewritten the whole instruction definition format.

1 files changed, 29 insertions, 15 deletions

diff --git a/plugins/arm/v7/opdefs/qsax_A88140.d b/plugins/arm/v7/opdefs/qsax_A88140.d
index df24cf8..1a9d204 100644
--- a/plugins/arm/v7/opdefs/qsax_A88140.d
+++ b/plugins/arm/v7/opdefs/qsax_A88140.d
@@ -2,7 +2,7 @@
 /* Chrysalide - Outil d'analyse de fichiers binaires
  * ##FILE## - traduction d'instructions ARMv7
  *
- * Copyright (C) 2015 Cyrille Bagard
+ * Copyright (C) 2017 Cyrille Bagard
  *
  *  This file is part of Chrysalide.
  *
@@ -23,19 +23,29 @@
 
 @title QSAX
 
-@desc Saturating Subtract and Add with Exchange exchanges the two halfwords of the second operand, performs one 16-bit integer subtraction and one 16-bit addition, saturates the results to the 16-bit signed integer range –215 ≤ x ≤ 215 – 1, and writes the results to the destination register.
+@id 139
+
+@desc {
+
+	Saturating Subtract and Add with Exchange exchanges the two halfwords of the second operand, performs one 16-bit integer subtraction and one 16-bit addition, saturates the results to the 16-bit signed integer range –215 ≤ x ≤ 215 – 1, and writes the results to the destination register.
+
+}
 
 @encoding (T1) {
 
 	@word 1 1 1 1 1 0 1 0 1 1 1 0 Rn(4) 1 1 1 1 Rd(4) 0 0 0 1 Rm(4)
 
-	@syntax <reg_D> <reg_N> <reg_M>
+	@syntax {
+
+		@conv {
 
-	@conv {
+			reg_D = Register(Rd)
+			reg_N = Register(Rn)
+			reg_M = Register(Rm)
 
-		reg_D = Register(Rd)
-		reg_N = Register(Rn)
-		reg_M = Register(Rm)
+		}
+
+		@asm qsax ?reg_D reg_N reg_M
 
 	}
 
@@ -45,19 +55,23 @@
 
 	@word cond(4) 0 1 1 0 0 0 1 0 Rn(4) Rd(4) 1 1 1 1 0 1 0 1 Rm(4)
 
-	@syntax <reg_D> <reg_N> <reg_M>
+	@syntax {
 
-	@conv {
+		@conv {
 
-		reg_D = Register(Rd)
-		reg_N = Register(Rn)
-		reg_M = Register(Rm)
+			reg_D = Register(Rd)
+			reg_N = Register(Rn)
+			reg_M = Register(Rm)
 
-	}
+		}
+
+		@asm qsax ?reg_D reg_N reg_M
+
+		@rules {
 
-	@rules {
+			check g_arm_instruction_set_cond(cond)
 
-		chk_call StoreCondition(cond)
+		}
 
 	}