diff options
author | Cyrille Bagard <nocbos@gmail.com> | 2015-01-14 20:59:18 (GMT) |
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committer | Cyrille Bagard <nocbos@gmail.com> | 2015-01-14 20:59:18 (GMT) |
commit | 0a028b306093746324eabdb94881083f9b7e61c1 (patch) | |
tree | 4af39fb6b4627e659319d8d4d40b62498a6080e8 /src/arch/arm/v7/opdefs/add_A889.d | |
parent | 8ef66a1e0225c9e00175fbaf3f3038f537de511f (diff) |
Supported new ARMv7 instructions and fixed a silent bug in a computed mask.
git-svn-id: svn://svn.gna.org/svn/chrysalide/trunk@454 abbe820e-26c8-41b2-8c08-b7b2b41f8b0a
Diffstat (limited to 'src/arch/arm/v7/opdefs/add_A889.d')
-rw-r--r-- | src/arch/arm/v7/opdefs/add_A889.d | 139 |
1 files changed, 139 insertions, 0 deletions
diff --git a/src/arch/arm/v7/opdefs/add_A889.d b/src/arch/arm/v7/opdefs/add_A889.d new file mode 100644 index 0000000..1f81776 --- /dev/null +++ b/src/arch/arm/v7/opdefs/add_A889.d @@ -0,0 +1,139 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2014 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title ADD (SP plus immediate) + +@encoding(t1) { + + @half 1 0 1 0 1 Rd(3) imm8(8) + + @syntax <Rd> <SP> <const> + + @conv { + + Rd = Register(Rd) + SP = Register(13) + const = ZeroExtend(imm8:'00', 10, 32); + + } + + @rules { + + //setflags = FALSE + + } + +} + +@encoding(t2) { + + @half 1 0 1 1 0 0 0 0 0 imm7(7) + + @syntax <SP1> <SP2> <const> + + @conv { + + SP1 = Register(13) + SP2 = Register(13) + const = ZeroExtend(imm7:'00', 9, 32); + + } + + @rules { + + //setflags = FALSE + + } + +} + +@encoding(T3) { + + @word 1 1 1 1 0 i(1) 0 1 0 0 0 S(1) 1 1 0 1 0 imm3(3) Rd(4) imm8(8) + + @syntax {S} ".W" <Rd> <SP> <const> + + @conv { + + S = SetFlags(S) + Rd = Register(Rd) + SP = Register(13) + const = ThumbExpandImm_C(i:imm3:imm8, i) + + } + + @rules { + + //if Rd == '1111' && S == '1' then SEE CMN (immediate); + //if d == 15 && S == '0' then UNPREDICTABLE; + + } + +} + +@encoding(T4) { + + @word 1 1 1 1 0 i(1) 0 1 0 0 0 S(1) 1 1 0 1 0 imm3(3) Rd(4) imm8(8) + + @syntax "addw" <Rd> <SP> <const> + + @conv { + + Rd = Register(Rd) + SP = Register(13) + const = ZeroExtend((i:imm3:imm8, 12, 32) + + } + + @rules { + + //if Rd == '1111' && S == '1' then SEE CMN (immediate); + //if d == 15 && S == '0' then UNPREDICTABLE; + + } + +} + +@encoding(A1) { + + @word cond(4) 0 0 1 0 1 0 0 S(1) 1 1 0 1 Rd(4) imm12(12) + + @syntax {S} {c} <Rd> <SP> <const> + + @conv { + + S = SetFlags(S) + c = Condition(cond) + Rd = Register(Rd) + SP = Register(13) + const = ARMExpandImm(imm12) + + } + + @rules { + + //if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions; + + } + +} |