diff options
| author | Cyrille Bagard <nocbos@gmail.com> | 2017-12-02 11:04:35 (GMT) |
|---|---|---|
| committer | Cyrille Bagard <nocbos@gmail.com> | 2017-12-02 11:04:35 (GMT) |
| commit | 2c988d3ec52cc4c949a35aca7ef335dac773df92 (patch) | |
| tree | fe650d2fc8ddceb606abdf0d2e14e5ef6596be82 /src/arch/arm/v7/opdefs/b_A8818.d | |
| parent | 23abef53590bf3dd6f88ff4dbe81e306abfa4386 (diff) | |
Created a plugin for the ARM support.
Diffstat (limited to 'src/arch/arm/v7/opdefs/b_A8818.d')
| -rw-r--r-- | src/arch/arm/v7/opdefs/b_A8818.d | 157 |
1 files changed, 0 insertions, 157 deletions
diff --git a/src/arch/arm/v7/opdefs/b_A8818.d b/src/arch/arm/v7/opdefs/b_A8818.d deleted file mode 100644 index 9e27753..0000000 --- a/src/arch/arm/v7/opdefs/b_A8818.d +++ /dev/null @@ -1,157 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title B - -@desc Branch causes a branch to a target address. - -@encoding (t1) { - - @half 1 1 0 1 cond(4) imm8(8) - - @syntax <imm32> - - @conv { - - imm32 = SignExtend(imm8:'0', imm8 & 0x80, 32) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - - @hooks { - - fetch = help_fetching_with_instruction_b_from_thumb - link = handle_arm_conditional_branch_as_link - post = post_process_branch_instructions - - } - -} - -@encoding (t2) { - - @half 1 1 1 0 0 imm11(11) - - @syntax <imm32> - - @conv { - - imm32 = SignExtend(imm11:'0', imm11 & 0x400, 32) - - } - - @hooks { - - fetch = help_fetching_with_instruction_b_from_thumb - link = handle_arm_conditional_branch_as_link - post = post_process_branch_instructions - - } - -} - -@encoding (T3) { - - @word 1 1 1 1 0 S(1) cond(4) imm6(6) 1 0 J1(1) 0 J2(1) imm11(11) - - @syntax ".W" <imm32> - - @conv { - - imm32 = SignExtend(S:J2:J1:imm6:imm11:'0', S & 0x1, 32) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - - @hooks { - - fetch = help_fetching_with_instruction_b_from_thumb - link = handle_arm_conditional_branch_as_link - post = post_process_branch_instructions - - } - -} - -@encoding (T4) { - - @word 1 1 1 1 0 S(1) imm10(10) 1 0 J1(1) 1 J2(1) imm11(11) - - @syntax ".W" <imm32> - - @conv { - - I1 = NOT(J1 EOR S) - I2 = NOT(J2 EOR S) - imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', S & 0x1, 32) - - } - - @hooks { - - fetch = help_fetching_with_instruction_b_from_thumb - link = handle_arm_conditional_branch_as_link - post = post_process_branch_instructions - - } - -} - -@encoding (A1) { - - @word cond(4) 1 0 1 0 imm24(24) - - @syntax <imm32> - - @conv { - - imm32 = SignExtend(imm24:'00', imm24 & 0x800000, 32) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - - @hooks { - - fetch = help_fetching_with_instruction_b_from_arm - link = handle_arm_conditional_branch_as_link - post = post_process_branch_instructions - - } - -} - |