diff options
| author | Cyrille Bagard <nocbos@gmail.com> | 2016-05-22 15:43:43 (GMT) | 
|---|---|---|
| committer | Cyrille Bagard <nocbos@gmail.com> | 2016-05-22 15:43:43 (GMT) | 
| commit | 7577eadd4e871d467f747c4927a1b1984d6a7606 (patch) | |
| tree | e72a2fd5c1619e60402a678b0559079ed267eab0 /src/arch/arm/v7/opdefs/cmn_A8834.d | |
| parent | 33aa90b022e7d711a733ca7eb62c0b285f974317 (diff) | |
Extended the compiler to transform all the new ARMv7 encoding definitions.
Diffstat (limited to 'src/arch/arm/v7/opdefs/cmn_A8834.d')
| -rw-r--r-- | src/arch/arm/v7/opdefs/cmn_A8834.d | 42 | 
1 files changed, 22 insertions, 20 deletions
diff --git a/src/arch/arm/v7/opdefs/cmn_A8834.d b/src/arch/arm/v7/opdefs/cmn_A8834.d index ff403f3..fc0b19f 100644 --- a/src/arch/arm/v7/opdefs/cmn_A8834.d +++ b/src/arch/arm/v7/opdefs/cmn_A8834.d @@ -2,7 +2,7 @@  /* Chrysalide - Outil d'analyse de fichiers binaires   * ##FILE## - traduction d'instructions ARMv7   * - * Copyright (C) 2014 Cyrille Bagard + * Copyright (C) 2015 Cyrille Bagard   *   *  This file is part of Chrysalide.   * @@ -23,39 +23,41 @@  @title CMN (immediate) -@encoding(T1) { +@desc Compare Negative (immediate) adds a register value and an immediate value. It updates the condition flags based on the result, and discards the result. -    @word 1 1 1 1 0 i(1) 0 1 0 0 0 1 Rn(4) 0 imm3(3) 1 1 1 1 imm8(8) +@encoding (T1) { -    @syntax <Rn> <const> +	@word 1 1 1 1 0 i(1) 0 1 0 0 0 1 Rn(4) 0 imm3(3) 1 1 1 1 imm8(8) -    @conv { +	@syntax <reg_N> <imm32> -        Rn = Register(Rn) -        const = ThumbExpandImm(i:imm3:imm8) +	@conv { -    } +		reg_N = Register(Rn) +		imm32 = ThumbExpandImm(i:imm3:imm8) -    @rules { +	} -        if (Rn == '1111') ; unpredictable +} -    } +@encoding (A1) { -} +	@word cond(4) 0 0 1 1 0 1 1 1 Rn(4) 0 0 0 0 imm12(12) -@encoding(A1) { +	@syntax <reg_N> <imm32> -    @word cond(4) 0 0 1 1 0 1 1 1 Rn(4) 0 0 0 0 imm12(12) +	@conv { -    @syntax {c} <Rn> <const> +		reg_N = Register(Rn) +		imm32 = ARMExpandImm(imm12) -    @conv { +	} -        c = Condition(cond) -        Rn = Register(Rn) -        const = ARMExpandImm(imm12) +	@rules { -    } +		chk_call StoreCondition(cond) + +	}  } +  | 
