diff options
| author | Cyrille Bagard <nocbos@gmail.com> | 2016-05-22 15:43:43 (GMT) |
|---|---|---|
| committer | Cyrille Bagard <nocbos@gmail.com> | 2016-05-22 15:43:43 (GMT) |
| commit | 7577eadd4e871d467f747c4927a1b1984d6a7606 (patch) | |
| tree | e72a2fd5c1619e60402a678b0559079ed267eab0 /src/arch/arm/v7/opdefs/eor_A8846.d | |
| parent | 33aa90b022e7d711a733ca7eb62c0b285f974317 (diff) | |
Extended the compiler to transform all the new ARMv7 encoding definitions.
Diffstat (limited to 'src/arch/arm/v7/opdefs/eor_A8846.d')
| -rw-r--r-- | src/arch/arm/v7/opdefs/eor_A8846.d | 56 |
1 files changed, 29 insertions, 27 deletions
diff --git a/src/arch/arm/v7/opdefs/eor_A8846.d b/src/arch/arm/v7/opdefs/eor_A8846.d index 2c71098..38dc858 100644 --- a/src/arch/arm/v7/opdefs/eor_A8846.d +++ b/src/arch/arm/v7/opdefs/eor_A8846.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2014 Cyrille Bagard + * Copyright (C) 2015 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,50 +23,52 @@ @title EOR (immediate) -@encoding(T1) { +@desc Bitwise Exclusive OR (immediate) performs a bitwise Exclusive OR of a register value and an immediate value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - @word 1 1 1 1 0 i(1) 0 0 1 0 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) +@encoding (T1) { - @syntax {S} <Rd> <Rn> <const> + @word 1 1 1 1 0 i(1) 0 0 1 0 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) - @conv { + @syntax <reg_D> <reg_N> <imm32> - S = SetFlags(S) - Rd = Register(Rd) - Rn = Register(Rn) - const = ThumbExpandImm_C(i:imm3:imm8, 0) + @conv { - } + reg_D = Register(Rd) + reg_N = Register(Rn) + setflags = (S == '1') + imm32 = ThumbExpandImm_C(i:imm3:imm8, 0) - @rules { + } - //if ((Rd == '1111') && (S == '1')) ; see TST (immediate) - //if ((d == 13) || ((d == 15) && (S == '0')) || (n IN {13,15})) ; unpredictable + @rules { - } + if (setflags); chk_call ExtendKeyword("s") + + } } -@encoding(A1) { +@encoding (A1) { - @word cond(4) 0 0 1 0 0 0 1 S(1) Rn(4) Rd(4) imm12(12) + @word cond(4) 0 0 1 0 0 0 1 S(1) Rn(4) Rd(4) imm12(12) - @syntax {S} {c} <Rd> <Rn> <const> + @syntax <reg_D> <reg_N> <imm32> - @conv { + @conv { - S = SetFlags(S) - c = Condition(cond) - Rd = Register(Rd) - Rn = Register(Rn) - const = ARMExpandImm_C(imm12, 0) + reg_D = Register(Rd) + reg_N = Register(Rn) + setflags = (S == '1') + imm32 = ARMExpandImm_C(imm12, 0) - } + } - @rules { + @rules { - //if ((Rd == '1111') && (S == '1')) ; see SUBS PC, LR and related instructions + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) - } + } } + |