Fixed and extended the support for ARM v7 instructions.

git-svn-id: svn://svn.gna.org/svn/chrysalide/trunk@542 abbe820e-26c8-41b2-8c08-b7b2b41f8b0a

1 files changed, 81 insertions, 0 deletions

diff --git a/src/arch/arm/v7/opdefs/ldrb_A8868.d b/src/arch/arm/v7/opdefs/ldrb_A8868.d
new file mode 100644
index 0000000..fdf3049
--- /dev/null
+++ b/src/arch/arm/v7/opdefs/ldrb_A8868.d
@@ -0,0 +1,81 @@
+
+/* Chrysalide - Outil d'analyse de fichiers binaires
+ * ##FILE## - traduction d'instructions ARMv7
+ *
+ * Copyright (C) 2014 Cyrille Bagard
+ *
+ *  This file is part of Chrysalide.
+ *
+ *  Chrysalide is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 3 of the License, or
+ *  (at your option) any later version.
+ *
+ *  Chrysalide is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Foobar.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+@title LDRB (immediate, ARM)
+
+@encoding(A11) {
+
+    @word cond(4) 0 1 0 1 U(1) 1 W(1) 1 Rn(4) Rt(4) imm12(12)
+
+    @syntax <Rgt> <access>
+
+    @conv {
+
+        Rgt = Register(Rt)
+        Rgn = Register(Rn)
+        imm32 = ZeroExtend(imm12, 12, 32);
+        access = MakeMemoryAccess(Rgn, imm32, U, W)
+
+    }
+
+    @rules {
+
+        //if Rt == '1111' && P == '1' && U == '0' && W == '0' then SEE PLD, PLDW (immediate);
+        //if Rn == '1111' then SEE LDRB (literal);
+        //if P == '1' && U == '1' && W == '0' then SEE LDRBT;
+        //if P == '0' && W == '0' then UNDEFINED;
+        //if t == 13 || (t == 15 && W == '1') || (wback && n == t) then UNPREDICTABLE;
+        if (Rt == '1111'); chk_call DefineAsReturn(1)
+
+    }
+
+}
+
+@encoding(A12) {
+
+    @word cond(4) 0 1 0 0 U(1) 1 W(1) 1 Rn(4) Rt(4) imm12(12)
+
+    @syntax <Rgt> <base> <offset>
+
+    @conv {
+
+        Rgt = Register(Rt)
+        Rgn = Register(Rn)
+        imm32 = ZeroExtend(imm12, 12, 32);
+        base = MakeMemoryNotIndexed(Rgn, W)
+        offset = MakeAccessOffset(U, imm32)
+
+    }
+
+    @rules {
+
+        //if Rt == '1111' && P == '1' && U == '0' && W == '0' then SEE PLD, PLDW (immediate);
+        //if Rn == '1111' then SEE LDRB (literal);
+        //if P == '1' && U == '1' && W == '0' then SEE LDRBT;
+        //if P == '0' && W == '0' then UNDEFINED;
+        //if t == 13 || (t == 15 && W == '1') || (wback && n == t) then UNPREDICTABLE;
+        if (Rt == '1111'); chk_call DefineAsReturn(1)
+
+    }
+
+}