diff options
| author | Cyrille Bagard <nocbos@gmail.com> | 2016-05-22 15:43:43 (GMT) |
|---|---|---|
| committer | Cyrille Bagard <nocbos@gmail.com> | 2016-05-22 15:43:43 (GMT) |
| commit | 7577eadd4e871d467f747c4927a1b1984d6a7606 (patch) | |
| tree | e72a2fd5c1619e60402a678b0559079ed267eab0 /src/arch/arm/v7/opdefs/lsr_A8896.d | |
| parent | 33aa90b022e7d711a733ca7eb62c0b285f974317 (diff) | |
Extended the compiler to transform all the new ARMv7 encoding definitions.
Diffstat (limited to 'src/arch/arm/v7/opdefs/lsr_A8896.d')
| -rw-r--r-- | src/arch/arm/v7/opdefs/lsr_A8896.d | 79 |
1 files changed, 36 insertions, 43 deletions
diff --git a/src/arch/arm/v7/opdefs/lsr_A8896.d b/src/arch/arm/v7/opdefs/lsr_A8896.d index 8e3f274..acb9e25 100644 --- a/src/arch/arm/v7/opdefs/lsr_A8896.d +++ b/src/arch/arm/v7/opdefs/lsr_A8896.d @@ -23,76 +23,69 @@ @title LSR (immediate) -@encoding(t1) { +@desc Logical Shift Right (immediate) shifts a register value right by an immediate number of bits, shifting in zeros, and writes the result to the destination register. It can optionally update the condition flags based on the result. - @half 0 0 0 0 1 imm5(5) Rm(3) Rd(3) +@encoding (t1) { - @syntax <Rgd> <Rgm> <shift> + @half 0 0 0 0 1 imm5(5) Rm(3) Rd(3) - @conv { + @syntax "lsrs" <reg_D> <reg_M> <shift_imm> - Rgd = Register(Rd) - Rgm = Register(Rm) - shift = DecodeImmShift(1, imm5) + @conv { - } + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_imm = DecodeImmShift('01', imm5) - @rules { - - if (imm5 == '00000') ; see MOV (register, Thumb) - //if (imm5 == '00000') ; see MOV (register) - - } + } } -@encoding(T2) { +@encoding (T2) { - @word 1 1 1 0 1 0 1 0 0 1 0 S(1) 1 1 1 1 0 imm3(3) Rd(4) imm2(2) 0 1 Rm(4) + @word 1 1 1 0 1 0 1 0 0 1 0 S(1) 1 1 1 1 0 imm3(3) Rd(4) imm2(2) 0 1 Rm(4) - @syntax {s} <Rgd> <Rgm> <shift> + @syntax <reg_D> <reg_M> <shift_imm> - @conv { + @conv { - S = SetFlags(S) - Rgd = Register(Rd) - Rgm = Register(Rm) - shift = DecodeImmShift(1, imm3:imm2) + reg_D = Register(Rd) + reg_M = Register(Rm) + setflags = (S == '1') + shift_imm = DecodeImmShift('01', imm3:imm2) - } + } - @rules { + @rules { - if ((imm3 == '000') && (imm2 == '00')) ; see MOV (register, Thumb) - //if ((imm3 == '000') && (imm2 == '00')) ; see MOV (register, Thumb) - //if (imm3:imm2) == '00000' then SEE MOV (register); - //if d IN {13,15} || m IN {13,15} then UNPREDICTABLE; + if (setflags); chk_call ExtendKeyword("s") + chk_call ExtendKeyword(".w") - } + } } -@encoding(A1) { +@encoding (A1) { - @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) imm5(5) 0 1 0 Rm(4) + @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) imm5(5) 0 1 0 Rm(4) - @syntax {S} {c} <Rgd> <Rgm> <shift> + @syntax <reg_D> <reg_M> <shift_imm> - @conv { + @conv { - S = SetFlags(S) - c = Condition(cond) - Rgd = Register(Rd) - Rgm = Register(Rm) - shift = DecodeImmShift(1, imm5) + reg_D = Register(Rd) + reg_M = Register(Rm) + setflags = (S == '1') + shift_imm = DecodeImmShift('01', imm5) - } + } - @rules { + @rules { - //if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions; - //if imm5 == '00000' then SEE MOV (register); + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) - } + } } + |