diff options
| author | Cyrille Bagard <nocbos@gmail.com> | 2016-05-22 15:43:43 (GMT) |
|---|---|---|
| committer | Cyrille Bagard <nocbos@gmail.com> | 2016-05-22 15:43:43 (GMT) |
| commit | 7577eadd4e871d467f747c4927a1b1984d6a7606 (patch) | |
| tree | e72a2fd5c1619e60402a678b0559079ed267eab0 /src/arch/arm/v7/opdefs/pop_A88132.d | |
| parent | 33aa90b022e7d711a733ca7eb62c0b285f974317 (diff) | |
Extended the compiler to transform all the new ARMv7 encoding definitions.
Diffstat (limited to 'src/arch/arm/v7/opdefs/pop_A88132.d')
| -rw-r--r-- | src/arch/arm/v7/opdefs/pop_A88132.d | 47 |
1 files changed, 22 insertions, 25 deletions
diff --git a/src/arch/arm/v7/opdefs/pop_A88132.d b/src/arch/arm/v7/opdefs/pop_A88132.d index 10e18a4..692aecb 100644 --- a/src/arch/arm/v7/opdefs/pop_A88132.d +++ b/src/arch/arm/v7/opdefs/pop_A88132.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2014 Cyrille Bagard + * Copyright (C) 2015 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,48 +23,45 @@ @title POP (ARM) -@encoding(A1) { +@desc Pop Multiple Registers loads multiple registers from the stack, loading from consecutive memory locations starting at the address in SP, and updates SP to point just above the loaded data. - @word cond(4) 1 0 0 0 1 0 1 1 1 1 0 1 register_list(16) +@encoding (A1) { - @syntax {c} <registers> + @word cond(4) 1 0 0 0 1 0 1 1 1 1 0 1 register_list(16) - @conv { + @syntax <registers> - c = Condition(cond) - registers = RegistersList(register_list) + @conv { - } + registers = RegistersList(register_list) - @rules { + } - //if BitCount(register_list) < 2 then SEE LDM / LDMIA / LDMFD; - //if registers<13> == '1' && ArchVersion() >= 7 then UNPREDICTABLE; - if (register_list & 0x8000) ; chk_call SetInsFlag(AIF_RETURN_POINT) + @rules { - } + chk_call StoreCondition(cond) + + } } -@encoding(A2) { +@encoding (A2) { - @word cond(4) 0 1 0 0 1 0 0 1 1 1 0 1 Rt(4) 0 0 0 0 0 0 0 0 0 1 0 0 + @word cond(4) 0 1 0 0 1 0 0 1 1 1 0 1 Rt(4) 0 0 0 0 0 0 0 0 0 1 0 0 - @syntax {c} <registers> + @syntax <registers> - @conv { + @conv { - c = Condition(cond) - Rgt = Register(Rt) - registers = ListFromRegister(Rgt) + registers = Zeros(16) - } + } - @rules { + @rules { - //if t == 13 then UNPREDICTABLE; - if (Rt == '1111') ; chk_call SetInsFlag(AIF_RETURN_POINT) + chk_call StoreCondition(cond) - } + } } + |