Update the list of handled ARM instructions

git-svn-id: svn://svn.gna.org/svn/chrysalide/trunk@423 abbe820e-26c8-41b2-8c08-b7b2b41f8b0a

1 files changed, 87 insertions, 0 deletions

diff --git a/src/arch/arm/v7/opdefs/rsb_A88152.d b/src/arch/arm/v7/opdefs/rsb_A88152.d
new file mode 100644
index 0000000..320d62e
--- /dev/null
+++ b/src/arch/arm/v7/opdefs/rsb_A88152.d
@@ -0,0 +1,87 @@
+
+/* Chrysalide - Outil d'analyse de fichiers binaires
+ * ##FILE## - traduction d'instructions ARMv7
+ *
+ * Copyright (C) 2014 Cyrille Bagard
+ *
+ *  This file is part of Chrysalide.
+ *
+ *  Chrysalide is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 3 of the License, or
+ *  (at your option) any later version.
+ *
+ *  Chrysalide is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Foobar.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+@title RSB (immediate)
+
+@encoding(T1) {
+
+    @half 0 1 0 0 0 0 1 0 0 1 Rn(3) Rd(3)
+
+    @syntax <Rd> <Rn> <zero>
+
+    @conv {
+
+        Rd = Register(Rd)
+        Rn = Register(Rn)
+        zero = Zeros(32)
+
+    }
+
+}
+
+@encoding(T2) {
+
+    @word 1 1 1 1 0 i(1) 0 1 1 1 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8)
+
+    @syntax {S} <Rd> <Rn> <const>
+
+    @conv {
+
+        S = SetFlags(S)
+        Rd = Register(Rd)
+        Rn = Register(Rn)
+        const = ThumbExpandImm(i:imm3:imm8)
+
+    }
+
+    @rules {
+
+        //if ((d IN {13,15}) || (n IN {13,15})) ; unpredictable
+
+    }
+
+}
+
+@encoding(A1) {
+
+    @word cond(4) 0 0 1 0 0 1 1 S(1) Rn(4) Rd(4) imm12(12)
+
+    @syntax {S} {c} <Rd> <Rn>
+
+    @conv {
+
+        S = SetFlags(S)
+        c = Condition(cond)
+        Rd = Register(Rd)
+        Rn = Register(Rn)
+        const = ARMExpandImm(imm12)
+
+    }
+
+    @rules {
+
+        //if ((Rd == '1111') && (S == '1')) ; see SUBS PC, LR and related instructions
+
+    }
+
+}