Extended the compiler to transform all the new ARMv7 encoding definitions.

1 files changed, 22 insertions, 20 deletions

diff --git a/src/arch/arm/v7/opdefs/tst_A88240.d b/src/arch/arm/v7/opdefs/tst_A88240.d
index 9d4a8f9..0ff5121 100644
--- a/src/arch/arm/v7/opdefs/tst_A88240.d
+++ b/src/arch/arm/v7/opdefs/tst_A88240.d
@@ -2,7 +2,7 @@
 /* Chrysalide - Outil d'analyse de fichiers binaires
  * ##FILE## - traduction d'instructions ARMv7
  *
- * Copyright (C) 2014 Cyrille Bagard
+ * Copyright (C) 2015 Cyrille Bagard
  *
  *  This file is part of Chrysalide.
  *
@@ -23,39 +23,41 @@
 
 @title TST (immediate)
 
-@encoding(T1) {
+@desc Test (immediate) performs a bitwise AND operation on a register value and an immediate value. It updates the condition flags based on the result, and discards the result.
 
-    @word 1 1 1 1 0 i(1) 0 0 0 0 0 1 Rn(4) 0 imm3(3) 1 1 1 1 imm8(8)
+@encoding (T1) {
 
-    @syntax <Rn> <const>
+	@word 1 1 1 1 0 i(1) 0 0 0 0 0 1 Rn(4) 0 imm3(3) 1 1 1 1 imm8(8)
 
-    @conv {
+	@syntax <reg_N> <imm32>
 
-        Rn = Register(Rn)
-        const = ThumbExpandImm_C(i:imm3:imm8, 0)
+	@conv {
 
-    }
+		reg_N = Register(Rn)
+		imm32 = ThumbExpandImm_C(i:imm3:imm8, 0)
 
-    @rules {
+	}
 
-        //if (n IN {13,15}) ; unpredictable
+}
 
-    }
+@encoding (A1) {
 
-}
+	@word cond(4) 0 0 1 1 0 0 0 1 Rn(4) 0 0 0 0 imm12(12)
 
-@encoding(A1) {
+	@syntax <reg_N> <imm32>
 
-    @word cond(4) 0 0 1 1 0 0 0 1 Rn(4) 0 0 0 0 imm12(12)
+	@conv {
 
-    @syntax {c} <Rn> <const>
+		reg_N = Register(Rn)
+		imm32 = ARMExpandImm_C(imm12, 0)
 
-    @conv {
+	}
 
-        c = Condition(cond)
-        Rn = Register(Rn)
-        const = ARMExpandImm_C(imm12, 0)
+	@rules {
 
-    }
+		chk_call StoreCondition(cond)
+
+	}
 
 }
+