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authorCyrille Bagard <nocbos@gmail.com>2017-12-02 11:04:35 (GMT)
committerCyrille Bagard <nocbos@gmail.com>2017-12-02 11:04:35 (GMT)
commit2c988d3ec52cc4c949a35aca7ef335dac773df92 (patch)
treefe650d2fc8ddceb606abdf0d2e14e5ef6596be82 /src/arch/arm/v7/opdefs/uqasx_A88260.d
parent23abef53590bf3dd6f88ff4dbe81e306abfa4386 (diff)
Created a plugin for the ARM support.
Diffstat (limited to 'src/arch/arm/v7/opdefs/uqasx_A88260.d')
-rw-r--r--src/arch/arm/v7/opdefs/uqasx_A88260.d65
1 files changed, 0 insertions, 65 deletions
diff --git a/src/arch/arm/v7/opdefs/uqasx_A88260.d b/src/arch/arm/v7/opdefs/uqasx_A88260.d
deleted file mode 100644
index 174b08c..0000000
--- a/src/arch/arm/v7/opdefs/uqasx_A88260.d
+++ /dev/null
@@ -1,65 +0,0 @@
-
-/* Chrysalide - Outil d'analyse de fichiers binaires
- * ##FILE## - traduction d'instructions ARMv7
- *
- * Copyright (C) 2015 Cyrille Bagard
- *
- * This file is part of Chrysalide.
- *
- * Chrysalide is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 3 of the License, or
- * (at your option) any later version.
- *
- * Chrysalide is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with Foobar. If not, see <http://www.gnu.org/licenses/>.
- */
-
-
-@title UQASX
-
-@desc Unsigned Saturating Add and Subtract with Exchange exchanges the two halfwords of the second operand, performs one unsigned 16-bit integer addition and one unsigned 16-bit subtraction, saturates the results to the 16-bit unsigned integer range 0 ≤ x ≤ 216 – 1, and writes the results to the destination register.
-
-@encoding (T1) {
-
- @word 1 1 1 1 1 0 1 0 1 0 1 0 Rn(4) 1 1 1 1 Rd(4) 0 1 0 1 Rm(4)
-
- @syntax <reg_D> <reg_N> <reg_M>
-
- @conv {
-
- reg_D = Register(Rd)
- reg_N = Register(Rn)
- reg_M = Register(Rm)
-
- }
-
-}
-
-@encoding (A1) {
-
- @word cond(4) 0 1 1 0 0 1 1 0 Rn(4) Rd(4) 1 1 1 1 0 0 1 1 Rm(4)
-
- @syntax <reg_D> <reg_N> <reg_M>
-
- @conv {
-
- reg_D = Register(Rd)
- reg_N = Register(Rn)
- reg_M = Register(Rm)
-
- }
-
- @rules {
-
- chk_call StoreCondition(cond)
-
- }
-
-}
-