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| author | Cyrille Bagard <nocbos@gmail.com> | 2014-11-25 08:05:22 (GMT) |
|---|---|---|
| committer | Cyrille Bagard <nocbos@gmail.com> | 2014-11-25 08:05:22 (GMT) |
| commit | 7a42f3772ab31bb9c756fc5c5c86c531c04b1d70 (patch) | |
| tree | 1dc6440b1a1dde546c5eccf7744e1df5128bd833 /src/arch/arm/v7/pseudo.c | |
| parent | 16f9d3b943e272112e01f5bc51e922e2ea2ddfb8 (diff) | |
Extended the range of supported ARMv7 instructions.
git-svn-id: svn://svn.gna.org/svn/chrysalide/trunk@427 abbe820e-26c8-41b2-8c08-b7b2b41f8b0a
Diffstat (limited to 'src/arch/arm/v7/pseudo.c')
| -rw-r--r-- | src/arch/arm/v7/pseudo.c | 113 |
1 files changed, 113 insertions, 0 deletions
diff --git a/src/arch/arm/v7/pseudo.c b/src/arch/arm/v7/pseudo.c index 4736309..aac8bb7 100644 --- a/src/arch/arm/v7/pseudo.c +++ b/src/arch/arm/v7/pseudo.c @@ -28,6 +28,9 @@ #include <libio.h> +#include "../../../common/bconst.h" + + /****************************************************************************** * * @@ -367,6 +370,116 @@ uint32_t armv7_arm_expand_imm(uint32_t imm12) /****************************************************************************** * * +* Paramètres : type2 = type de décallage encodé sur 2 bits. * +* imm5 = valeur de décallage entière sur 5 bits. * +* type = type de décallage à constituer. [OUT] * +* value = valeur pleine et entière à utiliser. [OUT] * +* * +* Description : Traduit la fonction 'DecodeImmShift'. * +* * +* Retour : Bilan de l'opération. * +* * +* Remarques : - * +* * +******************************************************************************/ + +bool armv7_decode_imm_shift(uint8_t type2, uint8_t imm5, SRType *type, uint32_t *value) +{ + bool result; /* Bilan à retourner */ + + result = true; + + switch (type2) + { + case b00: + *type = SRType_LSL; + *value = imm5; + break; + + case b01: + *type = SRType_LSR; + *value = (imm5 == 0 ? 32 : imm5); + break; + + case b10: + *type = SRType_ASR; + *value = (imm5 == 0 ? 32 : imm5); + break; + + case b11: + if (imm5 == 0) + { + *type = SRType_RRX; + *value = 1; + } + else + { + *type = SRType_ROR; + *value = imm5; + } + break; + + default: + result = false; + break; + + } + + return result; + +} + + +/****************************************************************************** +* * +* Paramètres : type2 = type de décallage encodé sur 2 bits. * +* type = type de décallage à constituer. [OUT] * +* * +* Description : Traduit la fonction 'DecodeRegShift'. * +* * +* Retour : Bilan de l'opération. * +* * +* Remarques : - * +* * +******************************************************************************/ + +bool armv7_decode_reg_shift(uint8_t type2, SRType *type) +{ + bool result; /* Bilan à retourner */ + + result = true; + + switch (type2) + { + case b00: + *type = SRType_LSL; + break; + + case b01: + *type = SRType_LSR; + break; + + case b10: + *type = SRType_ASR; + break; + + case b11: + *type = SRType_ROR; + break; + + default: + result = false; + break; + + } + + return result; + +} + + +/****************************************************************************** +* * * Paramètres : x = valeur sur 32 bits maximum à traiter. * * n = nombre de bits à prendre en compte. * * type = type d'opération à mener. * |