Got prepared for more ARMv7 opcodes.

8 files changed, 2000 insertions, 156 deletions

diff --git a/src/arch/arm/v7/arm.c b/src/arch/arm/v7/arm.c
index 176d171..b536770 100644
--- a/src/arch/arm/v7/arm.c
+++ b/src/arch/arm/v7/arm.c
@@ -24,6 +24,7 @@
 #include "arm.h"
 
 
+#include <assert.h>
 #include <stdint.h>
 
 
@@ -33,76 +34,71 @@
 
 
 
-
 /* Désassemble une instruction ARMv7 de données ou autre. */
 static GArchInstruction *process_armv7_arm_data_processing_and_miscellaneous_instructions(uint32_t);
 
-/* Désassemble une instruction ARMv7 de données de registre. */
+/* Désassemble une instruction ARMv7 liées au chapitre A5.2.1. */
 static GArchInstruction *process_armv7_arm_data_processing_register(uint32_t);
 
-/* Désassemble une instruction ARMv7 de données de immédiate. */
+/* Désassemble une instruction ARMv7 liées au chapitre A5.2.2. */
+static GArchInstruction *process_armv7_arm_data_processing_register_shifted_register(uint32_t);
+
+/* Désassemble une instruction ARMv7 liées au chapitre A5.2.3. */
 static GArchInstruction *process_armv7_arm_data_processing_immediate(uint32_t);
 
-/* Désassemble une instruction ARMv7 liées aux multiplications. */
+/* Désassemble une instruction ARMv7 liées au chapitre A5.2.5. */
 static GArchInstruction *process_armv7_arm_multiply_and_multiply_accumulate(uint32_t);
 
+/* Désassemble une instruction ARMv7 liées au chapitre A5.2.6. */
+static GArchInstruction *process_armv7_arm_saturating_addition_and_subtraction(uint32_t);
 
+/* Désassemble une instruction ARMv7 liées au chapitre A5.2.7. */
+static GArchInstruction *process_armv7_arm_halfword_multiply_and_multiply_accumulate(uint32_t);
 
-/* Désassemble une instruction ARMv7 de données ou autre. */
-static GArchInstruction *process_armv7_arm_load_store_word_and_unsigned_byte(uint32_t);
+/* Désassemble une instruction ARMv7 liées au chapitre A5.2.8. */
+static GArchInstruction *process_armv7_arm_extra_load_store_instructions(uint32_t);
 
+/* Désassemble une instruction ARMv7 liées au chapitre A5.2.9. */
+static GArchInstruction *process_armv7_arm_extra_load_store_instructions_unprivileged(uint32_t);
 
+/* Désassemble une instruction ARMv7 liées au chapitre A5.2.10. */
+static GArchInstruction *process_armv7_arm_synchronization_primitives(uint32_t);
 
-/* Désassemble une instruction ARMv7 de données ou autre. */
-static GArchInstruction *process_armv7_arm_media_instructions(uint32_t);
+/* Désassemble une instruction ARMv7 liées au chapitre A5.2.11. */
+static GArchInstruction *process_armv7_arm_msr_immediate_and_hints(uint32_t);
 
+/* Désassemble une instruction ARMv7 liées au chapitre A5.2.12. */
+static GArchInstruction *process_armv7_arm_miscellaneous_instructions(uint32_t);
 
+/* Désassemble une instruction ARMv7 liées au chapitre A5.3. */
+static GArchInstruction *process_armv7_arm_load_store_word_and_unsigned_byte(uint32_t);
 
-#define process_armv7_arm_parallel_addition_and_subtraction_signed(raw) NULL
-#define process_armv7_arm_parallel_addition_and_subtraction_unsigned(raw) NULL
-#define process_armv7_arm_signed_multiply_signed_and_unsigned_divide(raw) NULL
+/* Désassemble une instruction ARMv7 liées au chapitre A5.4. */
+static GArchInstruction *process_armv7_arm_media_instructions(uint32_t);
 
+/* Désassemble une instruction ARMv7 liées au chapitre A5.4.1. */
+static GArchInstruction *process_armv7_arm_parallel_addition_and_subtraction_signed(uint32_t);
 
+/* Désassemble une instruction ARMv7 liées au chapitre A5.4.2. */
+static GArchInstruction *process_armv7_arm_parallel_addition_and_subtraction_unsigned(uint32_t);
 
-/* Désassemble une instruction ARMv7 de données ou autre. */
+/* Désassemble une instruction ARMv7 liées au chapitre A5.4.3. */
 static GArchInstruction *process_armv7_arm_packing_unpacking_saturation_and_reversal(uint32_t);
 
+/* Désassemble une instruction ARMv7 liées au chapitre A5.4.4. */
+static GArchInstruction *process_armv7_arm_signed_multiply_signed_and_unsigned_divide(uint32_t);
 
-
-/* Désassemble une instruction ARMv7 de données ou autre. */
+/* Désassemble une instruction ARMv7 liées au chapitre A5.5. */
 static GArchInstruction *process_armv7_arm_branch_branch_with_link_and_block_data_transfer(uint32_t);
 
+/* Désassemble une instruction ARMv7 liées au chapitre A5.6. */
+static GArchInstruction *process_armv7_arm_coprocessor_instructions_and_supervisor_call(uint32_t);
 
+/* Désassemble une instruction ARMv7 liées au chapitre A5.7. */
+static GArchInstruction *process_armv7_arm_unconditional_instructions(uint32_t);
 
-// process_armv7_arm_instruction_set_encoding
-
-//#define process_armv7_arm_load_store_word_and_unsigned_byte(raw) NULL
-//#define process_armv7_arm_load_store_word_and_unsigned_byte(raw) NULL
-//#define process_armv7_arm_media_instructions(raw) NULL
-//#define process_armv7_arm_branch_branch_with_link_and_block_data_transfer(raw) NULL
-#define process_armv7_arm_coprocessor_instructions_and_Supervisor_call(raw) NULL
-#define process_armv7_arm_unconditional_instructions(raw) NULL
-
-
-// process_armv7_arm_data_processing_and_miscellaneous_instructions
-
-#define process_armv7_arm_data_processing_register_shifted_register(raw) NULL
-#define process_armv7_arm_extra_load_store_instructions(raw) NULL
-#define process_armv7_arm_miscellaneous_instructions(raw) NULL
-#define process_armv7_arm_halfword_multiply_and_multiply_accumulate(raw) NULL
-//#define process_armv7_arm_multiply_and_multiply_accumulate(raw) NULL
-#define process_armv7_arm_synchronization_primitives(raw) NULL
-#define process_armv7_arm_extra_load_store_instructions_unprivileged(raw) NULL
-#define process_armv7_arm_extra_load_store_instructions(raw) NULL
-//#define process_armv7_arm_data_processing_immediate(raw) NULL
-
-#define process_armv7_arm_msr_immediate_and_hints(raw) NULL
-
-
-// process_armv7_arm_data_processing_register
-
-
-
+/* Désassemble une instruction ARMv7 liées au chapitre A5.7.1. */
+static GArchInstruction *process_armv7_arm_memory_hints_advanced_simd_instructions_and_miscellaneous_instructions(uint32_t);
 
 
 
@@ -110,7 +106,7 @@ static GArchInstruction *process_armv7_arm_branch_branch_with_link_and_block_dat
 *                                                                             *
 *  Paramètres  : raw = donnée brute de 32 bits à désassembler.                *
 *                                                                             *
-*  Description : Désassemble une instruction ARMv7 classique.                 *
+*  Description : Désassemble une instruction ARMv7 liées au chapitre A5.1.    *
 *                                                                             *
 *  Retour      : Instruction mise en place ou NULL en cas d'échec.            *
 *                                                                             *
@@ -149,7 +145,7 @@ GArchInstruction *process_armv7_arm_instruction_set_encoding(uint32_t raw)
             if (op == b0)
                 result = process_armv7_arm_load_store_word_and_unsigned_byte(raw);
 
-            else
+            else/* if (op == b1)*/
                 result = process_armv7_arm_media_instructions(raw);
 
         }
@@ -158,7 +154,7 @@ GArchInstruction *process_armv7_arm_instruction_set_encoding(uint32_t raw)
             result = process_armv7_arm_branch_branch_with_link_and_block_data_transfer(raw);
 
         else if ((op1 & b110) == b110)
-            result = process_armv7_arm_coprocessor_instructions_and_Supervisor_call(raw);
+            result = process_armv7_arm_coprocessor_instructions_and_supervisor_call(raw);
 
     }
 
@@ -297,7 +293,7 @@ static GArchInstruction *process_armv7_arm_data_processing_and_miscellaneous_ins
 *                                                                             *
 *  Paramètres  : raw = donnée brute de 32 bits à désassembler.                *
 *                                                                             *
-*  Description : Désassemble une instruction ARMv7 de données de registre.    *
+*  Description : Désassemble une instruction ARMv7 liées au chapitre A5.2.1.  *
 *                                                                             *
 *  Retour      : Instruction mise en place ou NULL en cas d'échec.            *
 *                                                                             *
@@ -317,6 +313,8 @@ static GArchInstruction *process_armv7_arm_data_processing_register(uint32_t raw
      * § A5.2.1 Data-processing (register)
      */
 
+    if ((raw & 0x0e000010) != 0x00000000) return NULL;
+
     result = NULL;
 
     op = (raw >> 20) & 0x1f;
@@ -408,17 +406,112 @@ static GArchInstruction *process_armv7_arm_data_processing_register(uint32_t raw
 }
 
 
+/******************************************************************************
+*                                                                             *
+*  Paramètres  : raw = donnée brute de 32 bits à désassembler.                *
+*                                                                             *
+*  Description : Désassemble une instruction ARMv7 liées au chapitre A5.2.2.  *
+*                                                                             *
+*  Retour      : Instruction mise en place ou NULL en cas d'échec.            *
+*                                                                             *
+*  Remarques   : -                                                            *
+*                                                                             *
+******************************************************************************/
+
+static GArchInstruction *process_armv7_arm_data_processing_register_shifted_register(uint32_t raw)
+{
+    GArchInstruction *result;               /* Instruction à retourner     */
+    uint32_t op1;                           /* Champ 'op1' à retrouver     */
+    uint32_t op2;                           /* Champ 'op2' à retrouver     */
+
+    /**
+     * Suit les directives de :
+     * § A5.2.2 Data-processing (register-shifted register)
+     */
+
+    if ((raw & 0x0e000090) != 0x00000010) return NULL;
+
+    result = NULL;
+
+    op1 = (raw >> 20) & 0x1f;
+    op2 = (raw >> 5) & 0x3;
+
+    if ((op1 & b11110) == b00000)
+        result = armv7_read_arm_instr_and_register_shifted_register(raw);
+
+    else if ((op1 & b11110) == b00010)
+        result = armv7_read_arm_instr_eor_register_shifted_register(raw);
 
+    else if ((op1 & b11110) == b00100)
+        result = armv7_read_arm_instr_sub_register_shifted_register(raw);
 
+    else if ((op1 & b11110) == b00110)
+        result = armv7_read_arm_instr_rsb_register_shifted_register(raw);
 
+    else if ((op1 & b11110) == b01000)
+        result = armv7_read_arm_instr_add_register_shifted_register(raw);
 
+    else if ((op1 & b11110) == b01010)
+        result = armv7_read_arm_instr_adc_register_shifted_register(raw);
+
+    else if ((op1 & b11110) == b01100)
+        result = armv7_read_arm_instr_sbc_register_shifted_register(raw);
+
+    else if ((op1 & b11110) == b01110)
+        result = armv7_read_arm_instr_rsc_register_shifted_register(raw);
+
+#if 0
+    else if ((op1 & b11001) == b10000)
+        /* See Data-processing and miscellaneous instructions on page A5-196 */
+#endif
+
+    else if (op1 == b10001)
+        result = armv7_read_arm_instr_tst_register_shifted_register(raw);
+
+    else if (op1 == b10011)
+        result = armv7_read_arm_instr_teq_register_shifted_register(raw);
+
+    else if (op1 == b10101)
+        result = armv7_read_arm_instr_cmp_register_shifted_register(raw);
+
+    else if (op1 == b10111)
+        result = armv7_read_arm_instr_cmn_register_shifted_register(raw);
+
+    else if ((op1 & b11110) == b11000)
+        result = armv7_read_arm_instr_orr_register_shifted_register(raw);
+
+    else if ((op1 & b11110) == b11010)
+    {
+        if (op2 == b00)
+            result = armv7_read_arm_instr_lsl_register(raw);
+
+        else if (op2 == b01)
+            result = armv7_read_arm_instr_lsr_register(raw);
+
+        else if (op2 == b10)
+            result = armv7_read_arm_instr_asr_register(raw);
+
+        else if (op2 == b11)
+            result = armv7_read_arm_instr_ror_register(raw);
+
+    }
+
+    else if ((op1 & b11110) == b11100)
+        result = armv7_read_arm_instr_bic_register_shifted_register(raw);
+
+    else if ((op1 & b11110) == b11110)
+        result = armv7_read_arm_instr_mvn_register_shifted_register(raw);
+
+    return result;
+
+}
 
 
 /******************************************************************************
 *                                                                             *
 *  Paramètres  : raw = donnée brute de 32 bits à désassembler.                *
 *                                                                             *
-*  Description : Désassemble une instruction ARMv7 de données de immédiate.   *
+*  Description : Désassemble une instruction ARMv7 liées au chapitre A5.2.3.  *
 *                                                                             *
 *  Retour      : Instruction mise en place ou NULL en cas d'échec.            *
 *                                                                             *
@@ -437,6 +530,8 @@ static GArchInstruction *process_armv7_arm_data_processing_immediate(uint32_t ra
      * § A5.2.3 Data-processing (immediate)
      */
 
+    if ((raw & 0x0e000000) != 0x04000000) return NULL;
+
     result = NULL;
 
     op = (raw >> 20) & 0x1f;
@@ -514,21 +609,11 @@ static GArchInstruction *process_armv7_arm_data_processing_immediate(uint32_t ra
 }
 
 
-
-
-
-
-
-
-
-
-
-
 /******************************************************************************
 *                                                                             *
 *  Paramètres  : raw = donnée brute de 32 bits à désassembler.                *
 *                                                                             *
-*  Description : Désassemble une instruction ARMv7 liées aux multiplications. *
+*  Description : Désassemble une instruction ARMv7 liées au chapitre A5.2.5.  *
 *                                                                             *
 *  Retour      : Instruction mise en place ou NULL en cas d'échec.            *
 *                                                                             *
@@ -546,10 +631,9 @@ static GArchInstruction *process_armv7_arm_multiply_and_multiply_accumulate(uint
      * § A5.2.5 Multiply and multiply accumulate
      */
 
-    result = NULL;
+    if ((raw & 0x0f0000f0) != 0x00000090) return NULL;
 
-    if ((raw & 0x0f0000f0) != 0x00000090)
-        return NULL;
+    result = NULL;
 
     op = (raw >> 20) & 0xf;
 
@@ -588,17 +672,533 @@ static GArchInstruction *process_armv7_arm_multiply_and_multiply_accumulate(uint
 }
 
 
+/******************************************************************************
+*                                                                             *
+*  Paramètres  : raw = donnée brute de 32 bits à désassembler.                *
+*                                                                             *
+*  Description : Désassemble une instruction ARMv7 liées au chapitre A5.2.6.  *
+*                                                                             *
+*  Retour      : Instruction mise en place ou NULL en cas d'échec.            *
+*                                                                             *
+*  Remarques   : -                                                            *
+*                                                                             *
+******************************************************************************/
 
+static GArchInstruction *process_armv7_arm_saturating_addition_and_subtraction(uint32_t raw)
+{
+    GArchInstruction *result;               /* Instruction à retourner     */
+    uint32_t op;                            /* Champ 'op' à retrouver      */
 
+    /**
+     * Suit les directives de :
+     * § A5.2.6 Saturating addition and subtraction
+     */
 
+    if ((raw & 0x0f9000f0) != 0x01000050) return NULL;
 
+    result = NULL;
+
+    op = (raw >> 21) & 0x3;
+
+    if (op == b00)
+        result = armv7_read_arm_instr_qadd(raw);
+
+    else if (op == b01)
+        result = armv7_read_arm_instr_qsub(raw);
+
+    else if (op == b10)
+        result = armv7_read_arm_instr_qdadd(raw);
+
+    else if (op == b11)
+        result = armv7_read_arm_instr_qdsub(raw);
+
+    return result;
+
+}
 
 
 /******************************************************************************
 *                                                                             *
 *  Paramètres  : raw = donnée brute de 32 bits à désassembler.                *
 *                                                                             *
-*  Description : Désassemble une instruction ARMv7 de données ou autre.       *
+*  Description : Désassemble une instruction ARMv7 liées au chapitre A5.2.7.  *
+*                                                                             *
+*  Retour      : Instruction mise en place ou NULL en cas d'échec.            *
+*                                                                             *
+*  Remarques   : -                                                            *
+*                                                                             *
+******************************************************************************/
+
+static GArchInstruction *process_armv7_arm_halfword_multiply_and_multiply_accumulate(uint32_t raw)
+{
+    GArchInstruction *result;               /* Instruction à retourner     */
+    uint32_t op1;                           /* Champ 'op1' à retrouver     */
+    uint32_t op;                            /* Champ 'op' à retrouver      */
+
+    /**
+     * Suit les directives de :
+     * § A5.2.7 Halfword multiply and multiply accumulate
+     */
+
+    if ((raw & 0x0f900090) != 0x01000080) return NULL;
+
+    result = NULL;
+
+    op1 = (raw >> 21) & 0x3;
+    op = (raw >> 5) & 0x1;
+
+    if (op1 == b00)
+        result = armv7_read_arm_instr_smlabb_smlabt_smlatb_smlatt(raw);
+
+    else if (op1 == b01)
+    {
+        if (op == b0)
+            result = armv7_read_arm_instr_smlawb_smlawt(raw);
+
+        else/* if (op == b1)*/
+            result = armv7_read_arm_instr_smulwb_smulwt(raw);
+
+    }
+
+    else if (op1 == b10)
+        result = armv7_read_arm_instr_smlalbb_smlalbt_smlaltb_smlaltt(raw);
+
+    else if (op1 == b11)
+        result = armv7_read_arm_instr_smulbb_smulbt_smultb_smultt(raw);
+
+    return result;
+
+}
+
+
+/******************************************************************************
+*                                                                             *
+*  Paramètres  : raw = donnée brute de 32 bits à désassembler.                *
+*                                                                             *
+*  Description : Désassemble une instruction ARMv7 liées au chapitre A5.2.8.  *
+*                                                                             *
+*  Retour      : Instruction mise en place ou NULL en cas d'échec.            *
+*                                                                             *
+*  Remarques   : -                                                            *
+*                                                                             *
+******************************************************************************/
+
+static GArchInstruction *process_armv7_arm_extra_load_store_instructions(uint32_t raw)
+{
+    GArchInstruction *result;               /* Instruction à retourner     */
+    uint32_t op1;                           /* Champ 'op1' à retrouver     */
+    uint32_t rn;                            /* Champ 'rn' à retrouver      */
+    uint32_t op2;                           /* Champ 'op2' à retrouver     */
+
+    /**
+     * Suit les directives de :
+     * § A5.2.8 Extra load/store instructions
+     */
+
+    if ((raw & 0x0e000090) != 0x00000090) return NULL;
+
+    result = NULL;
+
+    op1 = (raw >> 20) & 0x1f;
+    rn = (raw >> 16) & 0xf;
+    op2 = (raw >> 5) & 0x3;
+
+    if (op2 == b01)
+    {
+        if ((op1 & b00101) == b00000)
+            result = armv7_read_arm_instr_strh_register(raw);
+
+        else if ((op1 & b00101) == b00001)
+            result = armv7_read_arm_instr_ldrh_register(raw);
+
+        else if ((op1 & b00101) == b00100)
+            result = armv7_read_arm_instr_strh_immediate_arm(raw);
+
+        else/* if ((op1 & b00101) == b00101)*/
+        {
+            if (rn == b1111)
+                result = armv7_read_arm_instr_ldrh_literal(raw);
+
+            else
+                result = armv7_read_arm_instr_ldrh_immediate_arm(raw);
+
+        }
+
+    }
+
+    else if (op2 == b10)
+    {
+        if ((op1 & b00101) == b00000)
+            result = armv7_read_arm_instr_ldrd_register(raw);
+
+        else if ((op1 & b00101) == b00001)
+            result = armv7_read_arm_instr_ldrsb_register(raw);
+
+        else if ((op1 & b00101) == b00100)
+        {
+            if (rn == b1111)
+                result = armv7_read_arm_instr_ldrd_literal(raw);
+
+            else
+                result = armv7_read_arm_instr_ldrd_immediate(raw);
+
+        }
+
+        else/* if ((op1 & b00101) == b00101)*/
+        {
+            if (rn == b1111)
+                result = armv7_read_arm_instr_ldrsb_literal(raw);
+
+            else
+                result = armv7_read_arm_instr_ldrsb_immediate(raw);
+
+        }
+
+    }
+
+    else if (op2 == b11)
+    {
+        if ((op1 & b00101) == b00000)
+            result = armv7_read_arm_instr_strd_register(raw);
+
+        else if ((op1 & b00101) == b00001)
+            result = armv7_read_arm_instr_ldrsh_register(raw);
+
+        else if ((op1 & b00101) == b00100)
+            result = armv7_read_arm_instr_strd_immediate(raw);
+
+        else/* if ((op1 & b00101) == b00101)*/
+        {
+            if (rn == b1111)
+                result = armv7_read_arm_instr_ldrsh_literal(raw);
+
+            else
+                result = armv7_read_arm_instr_ldrsh_immediate(raw);
+
+        }
+
+    }
+
+    return result;
+
+}
+
+
+/******************************************************************************
+*                                                                             *
+*  Paramètres  : raw = donnée brute de 32 bits à désassembler.                *
+*                                                                             *
+*  Description : Désassemble une instruction ARMv7 liées au chapitre A5.2.9.  *
+*                                                                             *
+*  Retour      : Instruction mise en place ou NULL en cas d'échec.            *
+*                                                                             *
+*  Remarques   : -                                                            *
+*                                                                             *
+******************************************************************************/
+
+static GArchInstruction *process_armv7_arm_extra_load_store_instructions_unprivileged(uint32_t raw)
+{
+    GArchInstruction *result;               /* Instruction à retourner     */
+    uint32_t op;                            /* Champ 'op' à retrouver      */
+    uint32_t op2;                           /* Champ 'op2' à retrouver     */
+
+    /**
+     * Suit les directives de :
+     * § A5.2.9 Extra load/store instructions, unprivileged
+     */
+
+    if ((raw & 0x0f200090) != 0x00200090) return NULL;
+
+    result = NULL;
+
+    op = (raw >> 20) & 0x1;
+    op2 = (raw >> 5) & 0x3;
+
+    if (op2 == b01)
+    {
+        if (op == b0)
+            result = armv7_read_arm_instr_strht(raw);
+
+        else/* if (op == b1)*/
+            result = armv7_read_arm_instr_ldrht(raw);
+
+    }
+
+    else if (op2 == b10)
+    {
+        if (op == b1)
+            result = armv7_read_arm_instr_ldrsbt(raw);
+
+    }
+
+    else if (op2 == b11)
+    {
+        if (op == b1)
+            result = armv7_read_arm_instr_ldrsht(raw);
+
+    }
+
+    return result;
+
+}
+
+
+/******************************************************************************
+*                                                                             *
+*  Paramètres  : raw = donnée brute de 32 bits à désassembler.                *
+*                                                                             *
+*  Description : Désassemble une instruction ARMv7 liées au chapitre A5.2.10. *
+*                                                                             *
+*  Retour      : Instruction mise en place ou NULL en cas d'échec.            *
+*                                                                             *
+*  Remarques   : -                                                            *
+*                                                                             *
+******************************************************************************/
+
+static GArchInstruction *process_armv7_arm_synchronization_primitives(uint32_t raw)
+{
+    GArchInstruction *result;               /* Instruction à retourner     */
+    uint32_t op;                            /* Champ 'op' à retrouver      */
+
+    /**
+     * Suit les directives de :
+     * § A5.2.10 Synchronization primitives
+     */
+
+    if ((raw & 0x0f0000f0) != 0x01000090) return NULL;
+
+    result = NULL;
+
+    op = (raw >> 20) & 0xf;
+
+    if ((op & b1011) == b0000)
+        result = armv7_read_arm_instr_swp_swpb(raw);
+
+    else if (op == b1000)
+        result = armv7_read_arm_instr_strex(raw);
+
+    else if (op == b1001)
+        result = armv7_read_arm_instr_ldrex(raw);
+
+    else if (op == b1010)
+        result = armv7_read_arm_instr_strexd(raw);
+
+    else if (op == b1011)
+        result = armv7_read_arm_instr_ldrexd(raw);
+
+    else if (op == b1100)
+        result = armv7_read_arm_instr_strexb(raw);
+
+    else if (op == b1101)
+        result = armv7_read_arm_instr_ldrexb(raw);
+
+    else if (op == b1110)
+        result = armv7_read_arm_instr_strexh(raw);
+
+    else if (op == b1111)
+        result = armv7_read_arm_instr_ldrexh(raw);
+
+    return result;
+
+}
+
+
+/******************************************************************************
+*                                                                             *
+*  Paramètres  : raw = donnée brute de 32 bits à désassembler.                *
+*                                                                             *
+*  Description : Désassemble une instruction ARMv7 liées au chapitre A5.2.11. *
+*                                                                             *
+*  Retour      : Instruction mise en place ou NULL en cas d'échec.            *
+*                                                                             *
+*  Remarques   : -                                                            *
+*                                                                             *
+******************************************************************************/
+
+static GArchInstruction *process_armv7_arm_msr_immediate_and_hints(uint32_t raw)
+{
+    GArchInstruction *result;               /* Instruction à retourner     */
+    uint32_t op;                            /* Champ 'op' à retrouver      */
+    uint32_t op1;                           /* Champ 'op1' à retrouver     */
+    uint32_t op2;                           /* Champ 'op2' à retrouver     */
+
+    /**
+     * Suit les directives de :
+     * § A5.2.11 MSR (immediate), and hints
+     */
+
+    if ((raw & 0x0fb00000) != 0x03200000) return NULL;
+
+    result = NULL;
+
+    op = (raw >> 22) & 0x1;
+    op1 = (raw >> 16) & 0xf;
+    op2 = (raw >> 0) & 0x1;
+
+    if (op == b0)
+    {
+        if (op1 == b0000)
+        {
+            if (op2 == b00000000)
+                result = armv7_read_arm_instr_nop(raw);
+
+            else if (op2 == b00000001)
+                result = armv7_read_arm_instr_yield(raw);
+
+            else if (op2 == b00000010)
+                result = armv7_read_arm_instr_wfe(raw);
+
+            else if (op2 == b00000011)
+                result = armv7_read_arm_instr_wfi(raw);
+
+            else if (op2 == b00000100)
+                result = armv7_read_arm_instr_sev(raw);
+
+            else if ((op2 & b11110000) == b11110000)
+                result = armv7_read_arm_instr_dbg(raw);
+
+        }
+
+        else if (op1 == b0100 || (op1 & b1011) == b1000)
+            result = armv7_read_arm_instr_msr_immediate_a8(raw);
+
+        else if ((op1 & b0011) == b0001 || (op1 & b0010) == b0010)
+            result = armv7_read_arm_instr_msr_immediate_b9(raw);
+
+    }
+
+    else/* if (op == b1)*/
+        result = armv7_read_arm_instr_msr_immediate_b9(raw);
+
+    return result;
+
+}
+
+
+/******************************************************************************
+*                                                                             *
+*  Paramètres  : raw = donnée brute de 32 bits à désassembler.                *
+*                                                                             *
+*  Description : Désassemble une instruction ARMv7 liées au chapitre A5.2.12. *
+*                                                                             *
+*  Retour      : Instruction mise en place ou NULL en cas d'échec.            *
+*                                                                             *
+*  Remarques   : -                                                            *
+*                                                                             *
+******************************************************************************/
+
+static GArchInstruction *process_armv7_arm_miscellaneous_instructions(uint32_t raw)
+{
+    GArchInstruction *result;               /* Instruction à retourner     */
+    uint32_t op;                            /* Champ 'op' à retrouver      */
+    uint32_t op1;                           /* Champ 'op1' à retrouver     */
+    uint32_t b;                             /* Champ 'b' à retrouver       */
+    uint32_t op2;                           /* Champ 'op2' à retrouver     */
+
+    /**
+     * Suit les directives de :
+     * § A5.2.12 Miscellaneous instructions
+     */
+
+    if ((raw & 0x0f900080) != 0x00100000) return NULL;
+
+    result = NULL;
+
+    op = (raw >> 21) & 0x3;
+    op1 = (raw >> 16) & 0xf;
+    b = (raw >> 9) & 0x1;
+    op2 = (raw >> 4) & 0x7;
+
+    if (op2 == b000)
+    {
+        if (b == b1)
+        {
+            if ((op & b01) == b00)
+                result = armv7_read_arm_instr_mrs_banked_register(raw);
+
+            else/* if ((op & b01) == b01)*/
+                result = armv7_read_arm_instr_msr_banked_register(raw);
+
+        }
+        else/* if (b == b0)*/
+        {
+            if ((op & b01) == b00)
+                result = armv7_read_arm_instr_mrs(raw);
+
+            else if (op == b01)
+            {
+                if ((op1 & b0011) == b0000)
+                    result = armv7_read_arm_instr_msr_register_a8(raw);
+
+                else if ((op1 & b0011) == b0001 || (op1 & b0010) == b0010)
+                    result = armv7_read_arm_instr_msr_register_b9(raw);
+
+            }
+
+            else if (op == b11)
+                result = armv7_read_arm_instr_msr_register_b9(raw);
+
+        }
+
+    }
+
+    else if (op2 == b001)
+    {
+        if (op == b01)
+            result = armv7_read_arm_instr_bx(raw);
+
+        else if (op == b11)
+            result = armv7_read_arm_instr_clz(raw);
+
+    }
+
+    else if (op2 == b010)
+    {
+        if (op == b01)
+            result = armv7_read_arm_instr_bxj(raw);
+
+    }
+
+    else if (op2 == b011)
+    {
+        if (op == b01)
+            result = armv7_read_arm_instr_blx_register(raw);
+
+    }
+
+    else if (op2 == b101)
+        result = process_armv7_arm_saturating_addition_and_subtraction(raw);
+
+    else if (op2 == b110)
+    {
+        if (op == b11)
+            result = armv7_read_arm_instr_eret(raw);
+
+    }
+
+    else if (op2 == b111)
+    {
+        if (op == b)
+            result = armv7_read_arm_instr_bkpt(raw);
+
+        else if (op == b)
+            result = armv7_read_arm_instr_hvc(raw);
+
+        else if (op == b)
+            result = armv7_read_arm_instr_smc_previously_smi(raw);
+
+    }
+
+    return result;
+
+}
+
+
+/******************************************************************************
+*                                                                             *
+*  Paramètres  : raw = donnée brute de 32 bits à désassembler.                *
+*                                                                             *
+*  Description : Désassemble une instruction ARMv7 liées au chapitre A5.3.    *
 *                                                                             *
 *  Retour      : Instruction mise en place ou NULL en cas d'échec.            *
 *                                                                             *
@@ -619,6 +1219,8 @@ static GArchInstruction *process_armv7_arm_load_store_word_and_unsigned_byte(uin
      * § A5.3 Load/store word and unsigned byte
      */
 
+    if ((raw & 0x0c000000) != 0x04000000) return NULL;
+
     result = NULL;
 
     a = (raw >> 25) & 0x1;
@@ -752,7 +1354,7 @@ static GArchInstruction *process_armv7_arm_load_store_word_and_unsigned_byte(uin
 *                                                                             *
 *  Paramètres  : raw = donnée brute de 32 bits à désassembler.                *
 *                                                                             *
-*  Description : Désassemble une instruction ARMv7 de données ou autre.       *
+*  Description : Désassemble une instruction ARMv7 liées au chapitre A5.4.    *
 *                                                                             *
 *  Retour      : Instruction mise en place ou NULL en cas d'échec.            *
 *                                                                             *
@@ -774,10 +1376,9 @@ static GArchInstruction *process_armv7_arm_media_instructions(uint32_t raw)
      * § A5.4 Media instructions
      */
 
-    result = NULL;
+    if ((raw & 0x0e000010) != 0x06000010) return NULL;
 
-    if ((raw & 0x0e000010) != 0x06000010)
-        return NULL;
+    result = NULL;
 
     cond = (raw >> 28) & 0xf;
     op1 = (raw >> 20) & 0x1f;
@@ -857,7 +1458,209 @@ static GArchInstruction *process_armv7_arm_media_instructions(uint32_t raw)
 *                                                                             *
 *  Paramètres  : raw = donnée brute de 32 bits à désassembler.                *
 *                                                                             *
-*  Description : Désassemble une instruction ARMv7 de données ou autre.       *
+*  Description : Désassemble une instruction ARMv7 liées au chapitre A5.4.1.  *
+*                                                                             *
+*  Retour      : Instruction mise en place ou NULL en cas d'échec.            *
+*                                                                             *
+*  Remarques   : -                                                            *
+*                                                                             *
+******************************************************************************/
+
+static GArchInstruction *process_armv7_arm_parallel_addition_and_subtraction_signed(uint32_t raw)
+{
+    GArchInstruction *result;               /* Instruction à retourner     */
+    uint32_t op1;                           /* Champ 'op1' à retrouver     */
+    uint32_t op2;                           /* Champ 'op2' à retrouver     */
+
+    /**
+     * Suit les directives de :
+     * § A5.4.1 Parallel addition and subtraction, signed
+     */
+
+    if ((raw & 0x0fc00010) != 0x06000010) return NULL;
+
+    result = NULL;
+
+    op1 = (raw >> 20) & 0x3;
+    op2 = (raw >> 5) & 0x7;
+
+    if (op1 == b01)
+    {
+        if (op2 == b000)
+            result = armv7_read_arm_instr_sadd16(raw);
+
+        else if (op2 == b001)
+            result = armv7_read_arm_instr_sasx(raw);
+
+        else if (op2 == b010)
+            result = armv7_read_arm_instr_ssax(raw);
+
+        else if (op2 == b011)
+            result = armv7_read_arm_instr_ssub16(raw);
+
+        else if (op2 == b100)
+            result = armv7_read_arm_instr_sadd8(raw);
+
+        else if (op2 == b111)
+            result = armv7_read_arm_instr_ssub8(raw);
+
+    }
+
+    else if (op1 == b10)
+    {
+        if (op2 == b000)
+            result = armv7_read_arm_instr_qadd16(raw);
+
+        else if (op2 == b001)
+            result = armv7_read_arm_instr_qasx(raw);
+
+        else if (op2 == b010)
+            result = armv7_read_arm_instr_qsax(raw);
+
+        else if (op2 == b011)
+            result = armv7_read_arm_instr_qsub16(raw);
+
+        else if (op2 == b100)
+            result = armv7_read_arm_instr_qadd8(raw);
+
+        else if (op2 == b111)
+            result = armv7_read_arm_instr_qsub8(raw);
+
+    }
+
+    else if (op1 == b11)
+    {
+        if (op2 == b000)
+            result = armv7_read_arm_instr_shadd16(raw);
+
+        else if (op2 == b001)
+            result = armv7_read_arm_instr_shasx(raw);
+
+        else if (op2 == b010)
+            result = armv7_read_arm_instr_shsax(raw);
+
+        else if (op2 == b011)
+            result = armv7_read_arm_instr_shsub16(raw);
+
+        else if (op2 == b100)
+            result = armv7_read_arm_instr_shadd8(raw);
+
+        else if (op2 == b111)
+            result = armv7_read_arm_instr_shsub8(raw);
+
+    }
+
+    return result;
+
+}
+
+
+/******************************************************************************
+*                                                                             *
+*  Paramètres  : raw = donnée brute de 32 bits à désassembler.                *
+*                                                                             *
+*  Description : Désassemble une instruction ARMv7 liées au chapitre A5.4.2.  *
+*                                                                             *
+*  Retour      : Instruction mise en place ou NULL en cas d'échec.            *
+*                                                                             *
+*  Remarques   : -                                                            *
+*                                                                             *
+******************************************************************************/
+
+static GArchInstruction *process_armv7_arm_parallel_addition_and_subtraction_unsigned(uint32_t raw)
+{
+    GArchInstruction *result;               /* Instruction à retourner     */
+    uint32_t op1;                           /* Champ 'op1' à retrouver     */
+    uint32_t op2;                           /* Champ 'op2' à retrouver     */
+
+    /**
+     * Suit les directives de :
+     * § A5.4.2 Parallel addition and subtraction, unsigned
+     */
+
+    if ((raw & 0x0fc00010) != 0x06400010) return NULL;
+
+    result = NULL;
+
+    op1 = (raw >> 20) & 0x3;
+    op2 = (raw >> 5) & 0x7;
+
+    if (op1 == b01)
+    {
+        if (op2 == b000)
+            result = armv7_read_arm_instr_uadd16(raw);
+
+        else if (op2 == b001)
+            result = armv7_read_arm_instr_uasx(raw);
+
+        else if (op2 == b010)
+            result = armv7_read_arm_instr_usax(raw);
+
+        else if (op2 == b011)
+            result = armv7_read_arm_instr_usub16(raw);
+
+        else if (op2 == b100)
+            result = armv7_read_arm_instr_uadd8(raw);
+
+        else if (op2 == b111)
+            result = armv7_read_arm_instr_usub8(raw);
+
+    }
+
+    else if (op1 == b10)
+    {
+        if (op2 == b000)
+            result = armv7_read_arm_instr_uqadd16(raw);
+
+        else if (op2 == b001)
+            result = armv7_read_arm_instr_uqasx(raw);
+
+        else if (op2 == b010)
+            result = armv7_read_arm_instr_uqsax(raw);
+
+        else if (op2 == b011)
+            result = armv7_read_arm_instr_uqsub16(raw);
+
+        else if (op2 == b100)
+            result = armv7_read_arm_instr_uqadd8(raw);
+
+        else if (op2 == b111)
+            result = armv7_read_arm_instr_uqsub8(raw);
+
+    }
+
+    else if (op1 == b11)
+    {
+        if (op2 == b000)
+            result = armv7_read_arm_instr_uhadd16(raw);
+
+        else if (op2 == b001)
+            result = armv7_read_arm_instr_uhasx(raw);
+
+        else if (op2 == b010)
+            result = armv7_read_arm_instr_uhsax(raw);
+
+        else if (op2 == b011)
+            result = armv7_read_arm_instr_uhsub16(raw);
+
+        else if (op2 == b100)
+            result = armv7_read_arm_instr_uhadd8(raw);
+
+        else if (op2 == b111)
+            result = armv7_read_arm_instr_uhsub8(raw);
+
+    }
+
+    return result;
+
+}
+
+
+/******************************************************************************
+*                                                                             *
+*  Paramètres  : raw = donnée brute de 32 bits à désassembler.                *
+*                                                                             *
+*  Description : Désassemble une instruction ARMv7 liées au chapitre A5.4.3.  *
 *                                                                             *
 *  Retour      : Instruction mise en place ou NULL en cas d'échec.            *
 *                                                                             *
@@ -877,10 +1680,9 @@ static GArchInstruction *process_armv7_arm_packing_unpacking_saturation_and_reve
      * § A5.4.3 Packing, unpacking, saturation, and reversal
      */
 
-    result = NULL;
+    if ((raw & 0x0f800010) != 0x06800010) return NULL;
 
-    if ((raw & 0x0f800010) != 0x06800010)
-        return NULL;
+    result = NULL;
 
     op1 = (raw >> 20) & 0x7;
     a = (raw >> 16) & 0xf;
@@ -1044,19 +1846,110 @@ static GArchInstruction *process_armv7_arm_packing_unpacking_saturation_and_reve
 }
 
 
+/******************************************************************************
+*                                                                             *
+*  Paramètres  : raw = donnée brute de 32 bits à désassembler.                *
+*                                                                             *
+*  Description : Désassemble une instruction ARMv7 liées au chapitre A5.4.4.  *
+*                                                                             *
+*  Retour      : Instruction mise en place ou NULL en cas d'échec.            *
+*                                                                             *
+*  Remarques   : -                                                            *
+*                                                                             *
+******************************************************************************/
+
+static GArchInstruction *process_armv7_arm_signed_multiply_signed_and_unsigned_divide(uint32_t raw)
+{
+    GArchInstruction *result;               /* Instruction à retourner     */
+    uint32_t op1;                           /* Champ 'op1' à retrouver     */
+    uint32_t a;                             /* Champ 'a' à retrouver       */
+    uint32_t op2;                           /* Champ 'op2' à retrouver     */
+
+    /**
+     * Suit les directives de :
+     * § A5.4.4 Signed multiply, signed and unsigned divide
+     */
+
+    if ((raw & 0x0f800010) != 0x07000010) return NULL;
+
+    result = NULL;
+
+    op1 = (raw >> 20) & 0x7;
+    a = (raw >> 12) & 0xf;
+    op2 = (raw >> 5) & 0x7;
+
+    if (op1 == b000)
+    {
+        if ((op2 & b110) == b000)
+        {
+            if (a != b1111)
+                result = armv7_read_arm_instr_smlad(raw);
+            else/* if (a == b1111)*/
+                result = armv7_read_arm_instr_smuad(raw);
+
+        }
+
+        else if ((op2 & b110) == b010)
+        {
+            if (a != b1111)
+                result = armv7_read_arm_instr_smlsd(raw);
+            else/* if (a == b1111)*/
+                result = armv7_read_arm_instr_smusd(raw);
+
+        }
+
+    }
 
+    else if (op1 == b001)
+    {
+        if (op2 == b000)
+            result = armv7_read_arm_instr_sdiv(raw);
+
+    }
+
+    else if (op1 == b011)
+    {
+        if (op2 == b000)
+            result = armv7_read_arm_instr_udiv(raw);
+
+    }
+
+    else if (op1 == b100)
+    {
+        if ((op2 & b110) == b000)
+            result = armv7_read_arm_instr_smlald(raw);
+
+        else if ((op2 & b110) == b010)
+            result = armv7_read_arm_instr_smlsld(raw);
+
+    }
+
+    else if (op1 == b101)
+    {
+        if ((op2 & b110) == b000)
+        {
+            if (a != b1111)
+                result = armv7_read_arm_instr_smmla(raw);
+            else/* if (a == b1111)*/
+                result = armv7_read_arm_instr_smmul(raw);
 
+        }
 
+        else if ((op2 & b110) == b110)
+            result = armv7_read_arm_instr_smmls(raw);
 
+    }
 
+    return result;
 
+}
 
 
 /******************************************************************************
 *                                                                             *
 *  Paramètres  : raw = donnée brute de 32 bits à désassembler.                *
 *                                                                             *
-*  Description : Désassemble une instruction ARMv7 de données ou autre.       *
+*  Description : Désassemble une instruction ARMv7 liées au chapitre A5.5.    *
 *                                                                             *
 *  Retour      : Instruction mise en place ou NULL en cas d'échec.            *
 *                                                                             *
@@ -1076,6 +1969,8 @@ static GArchInstruction *process_armv7_arm_branch_branch_with_link_and_block_dat
      * § A5.5 Branch, branch with link, and block data transferr
      */
 
+    if ((raw & 0x0c000000) != 0x08000000) return NULL;
+
     result = NULL;
 
     op = (raw >> 20) & 0x3f;
@@ -1142,3 +2037,297 @@ static GArchInstruction *process_armv7_arm_branch_branch_with_link_and_block_dat
     return result;
 
 }
+
+
+/******************************************************************************
+*                                                                             *
+*  Paramètres  : raw = donnée brute de 32 bits à désassembler.                *
+*                                                                             *
+*  Description : Désassemble une instruction ARMv7 liées au chapitre A5.6.    *
+*                                                                             *
+*  Retour      : Instruction mise en place ou NULL en cas d'échec.            *
+*                                                                             *
+*  Remarques   : -                                                            *
+*                                                                             *
+******************************************************************************/
+
+static GArchInstruction *process_armv7_arm_coprocessor_instructions_and_supervisor_call(uint32_t raw)
+{
+    GArchInstruction *result;               /* Instruction à retourner     */
+    uint32_t op1;                           /* Champ 'op1' à retrouver     */
+    uint32_t rn;                            /* Champ 'rn' à retrouver      */
+    uint32_t coproc;                        /* Champ 'coproc' à retrouver      */
+    uint32_t op;                            /* Champ 'op' à retrouver      */
+
+    /**
+     * Suit les directives de :
+     * § A5.6 Coprocessor instructions, and Supervisor Call
+     */
+
+    if ((raw & 0x0c000000) != 0x0c000000) return NULL;
+
+    result = NULL;
+
+    op1 = (raw >> 20) & 0x3f;
+    rn = (raw >> 16) & 0xf;
+    coproc = (raw >> 8) & 0xf;
+    op = (raw >> 4) & 0x1;
+
+    if ((op1 & b111110) == b000000)
+        /* UNDEFINED */
+        assert(false);
+
+    else if ((op1 & b110000) == b110000)
+        result = armv7_read_arm_instr_svc_previously_swi(raw);
+
+    else if ((coproc & b1110) != b1010)
+    {
+        if ((op1 & b100001) == b000000 && (op1 & b111011) != b000000)
+            result = armv7_read_arm_instr_stc_stc2(raw);
+
+        else if ((op1 & b100001) == b000001 && (op1 & b111011) != b000001)
+        {
+            if (rn != b1111)
+                result = armv7_read_arm_instr_ldc_ldc2_immediate(raw);
+            else
+                result = armv7_read_arm_instr_ldc_ldc2_literal(raw);
+
+        }
+
+        else if (op1 == b000100)
+            result = armv7_read_arm_instr_mcrr_mcrr2(raw);
+
+        else if (op1 == b000101)
+            result = armv7_read_arm_instr_mrrc_mrrc2(raw);
+
+
+        else if ((op1 & b110000) == b100000 && op == b0)
+            result = armv7_read_arm_instr_cdp_cdp2(raw);
+
+        else if ((op1 & b110001) == b100000 && op == b1)
+            result = armv7_read_arm_instr_mcr_mcr2(raw);
+
+        else if ((op1 & b110001) == b100001 && op == b1)
+            result = armv7_read_arm_instr_mrc_mrc2(raw);
+
+    }
+
+    else if ((coproc & b1110) == b1010)
+    {
+        /* TODO */
+
+    }
+
+    return result;
+
+}
+
+
+/******************************************************************************
+*                                                                             *
+*  Paramètres  : raw = donnée brute de 32 bits à désassembler.                *
+*                                                                             *
+*  Description : Désassemble une instruction ARMv7 liées au chapitre A5.7.    *
+*                                                                             *
+*  Retour      : Instruction mise en place ou NULL en cas d'échec.            *
+*                                                                             *
+*  Remarques   : -                                                            *
+*                                                                             *
+******************************************************************************/
+
+static GArchInstruction *process_armv7_arm_unconditional_instructions(uint32_t raw)
+{
+    GArchInstruction *result;               /* Instruction à retourner     */
+    uint32_t op1;                           /* Champ 'op1' à retrouver     */
+    uint32_t rn;                            /* Champ 'rn' à retrouver      */
+    uint32_t op;                            /* Champ 'op' à retrouver      */
+
+    /**
+     * Suit les directives de :
+     * § A5.7 Unconditional instructions
+     */
+
+    if ((raw & 0xf0000000) != 0xf0000000) return NULL;
+
+    result = NULL;
+
+    op1 = (raw >> 20) & 0xff;
+    rn = (raw >> 16) & 0xf;
+    op = (raw >> 4) & 0x1;
+
+    if ((op1 & b10000000) == b00000000)
+        result = process_armv7_arm_memory_hints_advanced_simd_instructions_and_miscellaneous_instructions(raw);
+
+    else if ((op1 & b11100101) == b10000100)
+        result = armv7_read_arm_instr_srs_arm(raw);
+
+    else if ((op1 & b11100101) == b10000001)
+        result = armv7_read_arm_instr_rfe(raw);
+
+    else if ((op1 & b11100000) == b10100000)
+        result = armv7_read_arm_instr_bl_blx_immediate(raw);
+
+    else if ((op1 & b11100001) == b11000000 && (op1 & b11111011) != b11000000)
+        result = armv7_read_arm_instr_stc_stc2(raw);
+
+    else if ((op1 & b11100001) == b11000001 && (op1 & b11111011) != b11000001)
+    {
+        if (rn != b1111)
+            result = armv7_read_arm_instr_ldc_ldc2_immediate(raw);
+        else/* if (rn == b1111)*/
+            result = armv7_read_arm_instr_ldc_ldc2_literal(raw);
+    }
+
+    else if (op1 == b11000100)
+        result = armv7_read_arm_instr_mcrr_mcrr2(raw);
+
+    else if (op1 == b11000101)
+        result = armv7_read_arm_instr_mrrc_mrrc2(raw);
+
+    else if ((op1 & b11110000) == b11100000 && op == b0)
+        result = armv7_read_arm_instr_cdp_cdp2(raw);
+
+    else if ((op1 & b11110001) == b11100000 && op == b1)
+        result = armv7_read_arm_instr_mcr_mcr2(raw);
+
+    else if ((op1 & b11110001) == b11100001 && op == b1)
+        result = armv7_read_arm_instr_mrc_mrc2(raw);
+
+    return result;
+
+}
+
+
+/******************************************************************************
+*                                                                             *
+*  Paramètres  : raw = donnée brute de 32 bits à désassembler.                *
+*                                                                             *
+*  Description : Désassemble une instruction ARMv7 liées au chapitre A5.7.1.  *
+*                                                                             *
+*  Retour      : Instruction mise en place ou NULL en cas d'échec.            *
+*                                                                             *
+*  Remarques   : -                                                            *
+*                                                                             *
+******************************************************************************/
+
+static GArchInstruction *process_armv7_arm_memory_hints_advanced_simd_instructions_and_miscellaneous_instructions(uint32_t raw)
+{
+    GArchInstruction *result;               /* Instruction à retourner     */
+    uint32_t op1;                           /* Champ 'op1' à retrouver     */
+    uint32_t rn;                            /* Champ 'rn' à retrouver      */
+    uint32_t op2;                           /* Champ 'op2' à retrouver     */
+
+    /**
+     * Suit les directives de :
+     * § A5.7.1 Memory hints, Advanced SIMD instructions, and miscellaneous instructions
+     */
+
+    if ((raw & 0xf8000000) != 0xf0000000) return NULL;
+
+    result = NULL;
+
+    op1 = (raw >> 20) & 0x7f;
+    rn = (raw >> 16) & 0xf;
+    op2 = (raw >> 4) & 0xf;
+
+    if (op1 == b0010000)
+    {
+        if ((op2 & b0010) == b0000 && (rn & b0001) == b0000)
+            result = armv7_read_arm_instr_cps_arm(raw);
+
+        else if (op2 == b0000 && (rn & b0001) == b0001)
+            result = armv7_read_arm_instr_cps_arm(raw);
+
+    }
+
+    else if ((op1 & b1100000) == b0100000)
+        /* Advanced SIMD data-processing instructions */
+        assert(false);
+
+    else if ((op1 & b1110001) == b1000000)
+        /* Advanced SIMD element or structure load/store instructions */
+        assert(false);
+
+    else if ((op1 & b1110111) == b1000001)
+        /* (treat as NOP */
+        assert(false);
+
+    else if ((op1 & b1110111) == b1000101)
+        result = armv7_read_arm_instr_pli_immediate_literal(raw);
+
+    else if ((op1 & b1110011) == b1000011)
+        /* UNPREDICTABLE */
+        assert(false);
+
+    else if ((op1 & b1110111) == b1010101)
+    {
+        if (rn != b1111)
+            result = armv7_read_arm_instr_pld_pldw_immediate(raw);
+        else
+            /* UNPREDICTABLE */
+            assert(false);
+
+    }
+
+    else if ((op1 & b1110111) == b1010101)
+    {
+        if (rn != b1111)
+            result = armv7_read_arm_instr_pld_pldw_immediate(raw);
+        else
+            result = armv7_read_arm_instr_pld_literal(raw);
+
+    }
+
+    else if (op1 == b1010011)
+        /* UNPREDICTABLE */
+        assert(false);
+
+    else if (op1 == b1010111)
+    {
+        if (op2 == b0000)
+            /* UNPREDICTABLE */
+            assert(false);
+
+        else if (op2 == b0001)
+            result = armv7_read_arm_instr_clrex(raw);
+
+        else if ((op2 & b1110) == b0010)
+            /* UNPREDICTABLE */
+            assert(false);
+
+        else if (op2 == b0100)
+            result = armv7_read_arm_instr_dsb(raw);
+
+        else if (op2 == b0101)
+            result = armv7_read_arm_instr_dmd(raw);
+
+        else if (op2 == b0110)
+            result = armv7_read_arm_instr_isb(raw);
+
+        else if (op2 == b0111)
+            /* UNPREDICTABLE */
+            assert(false);
+
+        else if ((op2 & b1000) == b1000)
+            /* UNPREDICTABLE */
+            assert(false);
+
+    }
+
+    else if ((op1 & b1111011) == b1011011)
+        /* UNPREDICTABLE */
+        assert(false);
+
+    else if ((op1 & b1110111) == b1100001 && (op2 & b0001) == b0000)
+        /* (treat as NOP */
+        assert(false);
+
+    else if ((op1 & b1110111) == b1100101 && (op2 & b0001) == b0000)
+        result = armv7_read_arm_instr_pli_register(raw);
+
+    else if ((op1 & b1110111) == b1110001 && (op2 & b0001) == b0000)
+        result = armv7_read_arm_instr_pld_pldw_register(raw);
+
+    return result;
+
+}
diff --git a/src/arch/arm/v7/arm.h b/src/arch/arm/v7/arm.h
index 2a751a5..5fcedc3 100644
--- a/src/arch/arm/v7/arm.h
+++ b/src/arch/arm/v7/arm.h
@@ -29,7 +29,7 @@
 
 
 
-/* Désassemble une instruction ARMv7 classique. */
+/* Désassemble une instruction ARMv7 liées au chapitre A5.1. */
 GArchInstruction *process_armv7_arm_instruction_set_encoding(uint32_t raw);
 
 
diff --git a/src/arch/arm/v7/opcodes/opcodes_tmp_arm.h b/src/arch/arm/v7/opcodes/opcodes_tmp_arm.h
index 719d3c3..c4cf3b2 100644
--- a/src/arch/arm/v7/opcodes/opcodes_tmp_arm.h
+++ b/src/arch/arm/v7/opcodes/opcodes_tmp_arm.h
@@ -1,7 +1,29 @@
 #ifndef arm_def_tmp_h
 #define arm_def_tmp_h
+#define armv7_read_arm_instr_adc_register_shifted_register(r) NULL
+#define armv7_read_arm_instr_add_register_shifted_register(r) NULL
+#define armv7_read_arm_instr_and_register_shifted_register(r) NULL
+#define armv7_read_arm_instr_asr_register(r) NULL
 #define armv7_read_arm_instr_bfc(r) NULL
 #define armv7_read_arm_instr_bfi(r) NULL
+#define armv7_read_arm_instr_bic_register_shifted_register(r) NULL
+#define armv7_read_arm_instr_bkpt(r) NULL
+#define armv7_read_arm_instr_bxj(r) NULL
+#define armv7_read_arm_instr_cdp_cdp2(r) NULL
+#define armv7_read_arm_instr_clrex(r) NULL
+#define armv7_read_arm_instr_clz(r) NULL
+#define armv7_read_arm_instr_cmn_register_shifted_register(r) NULL
+#define armv7_read_arm_instr_cmp_register_shifted_register(r) NULL
+#define armv7_read_arm_instr_cps_arm(r) NULL
+#define armv7_read_arm_instr_dbg(r) NULL
+#define armv7_read_arm_instr_dmd(r) NULL
+#define armv7_read_arm_instr_dsb(r) NULL
+#define armv7_read_arm_instr_eor_register_shifted_register(r) NULL
+#define armv7_read_arm_instr_eret(r) NULL
+#define armv7_read_arm_instr_hvc(r) NULL
+#define armv7_read_arm_instr_isb(r) NULL
+#define armv7_read_arm_instr_ldc_ldc2_immediate(r) NULL
+#define armv7_read_arm_instr_ldc_ldc2_literal(r) NULL
 #define armv7_read_arm_instr_ldmda_ldmfa(r) NULL
 #define armv7_read_arm_instr_ldmdb_ldmea(r) NULL
 #define armv7_read_arm_instr_ldm_exception_return(r) NULL
@@ -10,41 +32,161 @@
 #define armv7_read_arm_instr_ldm_user_registers(r) NULL
 #define armv7_read_arm_instr_ldrb_literal(r) NULL
 #define armv7_read_arm_instr_ldrbt(r) NULL
+#define armv7_read_arm_instr_ldrd_immediate(r) NULL
+#define armv7_read_arm_instr_ldrd_literal(r) NULL
+#define armv7_read_arm_instr_ldrd_register(r) NULL
+#define armv7_read_arm_instr_ldrex(r) NULL
+#define armv7_read_arm_instr_ldrexb(r) NULL
+#define armv7_read_arm_instr_ldrexd(r) NULL
+#define armv7_read_arm_instr_ldrexh(r) NULL
+#define armv7_read_arm_instr_ldrh_immediate_arm(r) NULL
+#define armv7_read_arm_instr_ldrh_literal(r) NULL
+#define armv7_read_arm_instr_ldrh_register(r) NULL
+#define armv7_read_arm_instr_ldrht(r) NULL
 #define armv7_read_arm_instr_ldr_register(r) NULL
+#define armv7_read_arm_instr_ldrsb_immediate(r) NULL
+#define armv7_read_arm_instr_ldrsb_literal(r) NULL
+#define armv7_read_arm_instr_ldrsb_register(r) NULL
+#define armv7_read_arm_instr_ldrsbt(r) NULL
+#define armv7_read_arm_instr_ldrsh_immediate(r) NULL
+#define armv7_read_arm_instr_ldrsh_literal(r) NULL
+#define armv7_read_arm_instr_ldrsh_register(r) NULL
+#define armv7_read_arm_instr_ldrsht(r) NULL
 #define armv7_read_arm_instr_ldrt(r) NULL
+#define armv7_read_arm_instr_lsl_register(r) NULL
+#define armv7_read_arm_instr_lsr_register(r) NULL
+#define armv7_read_arm_instr_mcr_mcr2(r) NULL
+#define armv7_read_arm_instr_mcrr_mcrr2(r) NULL
+#define armv7_read_arm_instr_mrc_mrc2(r) NULL
+#define armv7_read_arm_instr_mrrc_mrrc2(r) NULL
+#define armv7_read_arm_instr_mrs(r) NULL
+#define armv7_read_arm_instr_mrs_banked_register(r) NULL
+#define armv7_read_arm_instr_msr_banked_register(r) NULL
+#define armv7_read_arm_instr_msr_immediate_a8(r) NULL
+#define armv7_read_arm_instr_msr_immediate_b9(r) NULL
+#define armv7_read_arm_instr_msr_register_a8(r) NULL
+#define armv7_read_arm_instr_msr_register_b9(r) NULL
+#define armv7_read_arm_instr_mvn_register_shifted_register(r) NULL
+#define armv7_read_arm_instr_orr_register_shifted_register(r) NULL
 #define armv7_read_arm_instr_pkh(r) NULL
+#define armv7_read_arm_instr_pld_literal(r) NULL
+#define armv7_read_arm_instr_pld_pldw_immediate(r) NULL
+#define armv7_read_arm_instr_pld_pldw_register(r) NULL
+#define armv7_read_arm_instr_pli_immediate_literal(r) NULL
+#define armv7_read_arm_instr_pli_register(r) NULL
+#define armv7_read_arm_instr_qadd(r) NULL
+#define armv7_read_arm_instr_qadd16(r) NULL
+#define armv7_read_arm_instr_qadd8(r) NULL
+#define armv7_read_arm_instr_qasx(r) NULL
+#define armv7_read_arm_instr_qdadd(r) NULL
+#define armv7_read_arm_instr_qdsub(r) NULL
+#define armv7_read_arm_instr_qsax(r) NULL
+#define armv7_read_arm_instr_qsub(r) NULL
+#define armv7_read_arm_instr_qsub16(r) NULL
+#define armv7_read_arm_instr_qsub8(r) NULL
 #define armv7_read_arm_instr_rbit(r) NULL
 #define armv7_read_arm_instr_rev(r) NULL
 #define armv7_read_arm_instr_rev16(r) NULL
 #define armv7_read_arm_instr_revsh(r) NULL
+#define armv7_read_arm_instr_rfe(r) NULL
 #define armv7_read_arm_instr_ror_immediate(r) NULL
+#define armv7_read_arm_instr_ror_register(r) NULL
 #define armv7_read_arm_instr_rrx(r) NULL
+#define armv7_read_arm_instr_rsb_register_shifted_register(r) NULL
+#define armv7_read_arm_instr_rsc_register_shifted_register(r) NULL
+#define armv7_read_arm_instr_sadd16(r) NULL
+#define armv7_read_arm_instr_sadd8(r) NULL
+#define armv7_read_arm_instr_sasx(r) NULL
+#define armv7_read_arm_instr_sbc_register_shifted_register(r) NULL
 #define armv7_read_arm_instr_sbfx(r) NULL
+#define armv7_read_arm_instr_sdiv(r) NULL
 #define armv7_read_arm_instr_sel(r) NULL
+#define armv7_read_arm_instr_sev(r) NULL
+#define armv7_read_arm_instr_shadd16(r) NULL
+#define armv7_read_arm_instr_shadd8(r) NULL
+#define armv7_read_arm_instr_shasx(r) NULL
+#define armv7_read_arm_instr_shsax(r) NULL
+#define armv7_read_arm_instr_shsub16(r) NULL
+#define armv7_read_arm_instr_shsub8(r) NULL
+#define armv7_read_arm_instr_smc_previously_smi(r) NULL
+#define armv7_read_arm_instr_smlabb_smlabt_smlatb_smlatt(r) NULL
+#define armv7_read_arm_instr_smlad(r) NULL
+#define armv7_read_arm_instr_smlalbb_smlalbt_smlaltb_smlaltt(r) NULL
+#define armv7_read_arm_instr_smlald(r) NULL
+#define armv7_read_arm_instr_smlawb_smlawt(r) NULL
+#define armv7_read_arm_instr_smlsd(r) NULL
+#define armv7_read_arm_instr_smlsld(r) NULL
+#define armv7_read_arm_instr_smmla(r) NULL
+#define armv7_read_arm_instr_smmls(r) NULL
+#define armv7_read_arm_instr_smmul(r) NULL
+#define armv7_read_arm_instr_smuad(r) NULL
+#define armv7_read_arm_instr_smulbb_smulbt_smultb_smultt(r) NULL
+#define armv7_read_arm_instr_smulwb_smulwt(r) NULL
+#define armv7_read_arm_instr_smusd(r) NULL
+#define armv7_read_arm_instr_srs_arm(r) NULL
 #define armv7_read_arm_instr_ssat(r) NULL
 #define armv7_read_arm_instr_ssat16(r) NULL
+#define armv7_read_arm_instr_ssax(r) NULL
+#define armv7_read_arm_instr_ssub16(r) NULL
+#define armv7_read_arm_instr_ssub8(r) NULL
+#define armv7_read_arm_instr_stc_stc2(r) NULL
 #define armv7_read_arm_instr_stmda_stmed(r) NULL
 #define armv7_read_arm_instr_stmdb_stmfd(r) NULL
 #define armv7_read_arm_instr_stmib_stmfa(r) NULL
 #define armv7_read_arm_instr_stm_stmia_stmea(r) NULL
 #define armv7_read_arm_instr_stm_user_registers(r) NULL
 #define armv7_read_arm_instr_strbt(r) NULL
+#define armv7_read_arm_instr_strd_immediate(r) NULL
+#define armv7_read_arm_instr_strd_register(r) NULL
+#define armv7_read_arm_instr_strex(r) NULL
+#define armv7_read_arm_instr_strexb(r) NULL
+#define armv7_read_arm_instr_strexd(r) NULL
+#define armv7_read_arm_instr_strexh(r) NULL
+#define armv7_read_arm_instr_strh_immediate_arm(r) NULL
+#define armv7_read_arm_instr_strh_register(r) NULL
+#define armv7_read_arm_instr_strht(r) NULL
 #define armv7_read_arm_instr_str_register(r) NULL
 #define armv7_read_arm_instr_strt(r) NULL
+#define armv7_read_arm_instr_sub_register_shifted_register(r) NULL
+#define armv7_read_arm_instr_svc_previously_swi(r) NULL
+#define armv7_read_arm_instr_swp_swpb(r) NULL
 #define armv7_read_arm_instr_sxtab(r) NULL
 #define armv7_read_arm_instr_sxtab16(r) NULL
 #define armv7_read_arm_instr_sxtah(r) NULL
 #define armv7_read_arm_instr_sxtb(r) NULL
 #define armv7_read_arm_instr_sxtb16(r) NULL
 #define armv7_read_arm_instr_sxth(r) NULL
+#define armv7_read_arm_instr_teq_register_shifted_register(r) NULL
+#define armv7_read_arm_instr_tst_register_shifted_register(r) NULL
+#define armv7_read_arm_instr_uadd16(r) NULL
+#define armv7_read_arm_instr_uadd8(r) NULL
+#define armv7_read_arm_instr_uasx(r) NULL
 #define armv7_read_arm_instr_ubfx(r) NULL
+#define armv7_read_arm_instr_udiv(r) NULL
+#define armv7_read_arm_instr_uhadd16(r) NULL
+#define armv7_read_arm_instr_uhadd8(r) NULL
+#define armv7_read_arm_instr_uhasx(r) NULL
+#define armv7_read_arm_instr_uhsax(r) NULL
+#define armv7_read_arm_instr_uhsub16(r) NULL
+#define armv7_read_arm_instr_uhsub8(r) NULL
+#define armv7_read_arm_instr_uqadd16(r) NULL
+#define armv7_read_arm_instr_uqadd8(r) NULL
+#define armv7_read_arm_instr_uqasx(r) NULL
+#define armv7_read_arm_instr_uqsax(r) NULL
+#define armv7_read_arm_instr_uqsub16(r) NULL
+#define armv7_read_arm_instr_uqsub8(r) NULL
 #define armv7_read_arm_instr_usad8(r) NULL
 #define armv7_read_arm_instr_usada8(r) NULL
 #define armv7_read_arm_instr_usat(r) NULL
 #define armv7_read_arm_instr_usat16(r) NULL
+#define armv7_read_arm_instr_usax(r) NULL
+#define armv7_read_arm_instr_usub16(r) NULL
+#define armv7_read_arm_instr_usub8(r) NULL
 #define armv7_read_arm_instr_uxtab(r) NULL
 #define armv7_read_arm_instr_uxtab16(r) NULL
 #define armv7_read_arm_instr_uxtah(r) NULL
 #define armv7_read_arm_instr_uxtb16(r) NULL
 #define armv7_read_arm_instr_uxth(r) NULL
+#define armv7_read_arm_instr_wfe(r) NULL
+#define armv7_read_arm_instr_wfi(r) NULL
 #endif
diff --git a/src/arch/arm/v7/opcodes/opcodes_tmp_thumb_32.h b/src/arch/arm/v7/opcodes/opcodes_tmp_thumb_32.h
index 7510b20..1970369 100644
--- a/src/arch/arm/v7/opcodes/opcodes_tmp_thumb_32.h
+++ b/src/arch/arm/v7/opcodes/opcodes_tmp_thumb_32.h
@@ -6,6 +6,7 @@
 #define armv7_read_thumb_32_instr_b_mrs(r) NULL
 #define armv7_read_thumb_32_instr_b_msr_register(r) NULL
 #define armv7_read_thumb_32_instr_bxj(r) NULL
+#define armv7_read_thumb_32_instr_cdp_cdp2(r) NULL
 #define armv7_read_thumb_32_instr_clrex(r) NULL
 #define armv7_read_thumb_32_instr_clz(r) NULL
 #define armv7_read_thumb_32_instr_cps_thumb(r) NULL
@@ -16,17 +17,37 @@
 #define armv7_read_thumb_32_instr_eret(r) NULL
 #define armv7_read_thumb_32_instr_hvc(r) NULL
 #define armv7_read_thumb_32_instr_isb(r) NULL
+#define armv7_read_thumb_32_instr_ldc_ldc2_immediate(r) NULL
+#define armv7_read_thumb_32_instr_ldc_ldc2_literal(r) NULL
 #define armv7_read_thumb_32_instr_ldmdb_ldmea(r) NULL
 #define armv7_read_thumb_32_instr_ldm_ldmia_ldmfd_thumb(r) NULL
 #define armv7_read_thumb_32_instr_ldrb_literal(r) NULL
 #define armv7_read_thumb_32_instr_ldrbt(r) NULL
+#define armv7_read_thumb_32_instr_ldrd_immediate(r) NULL
+#define armv7_read_thumb_32_instr_ldrd_literal(r) NULL
+#define armv7_read_thumb_32_instr_ldrex(r) NULL
+#define armv7_read_thumb_32_instr_ldrexb(r) NULL
+#define armv7_read_thumb_32_instr_ldrexd(r) NULL
+#define armv7_read_thumb_32_instr_ldrexh(r) NULL
+#define armv7_read_thumb_32_instr_ldrh_immediate_thumb(r) NULL
+#define armv7_read_thumb_32_instr_ldrh_literal(r) NULL
+#define armv7_read_thumb_32_instr_ldrh_register(r) NULL
+#define armv7_read_thumb_32_instr_ldrht(r) NULL
 #define armv7_read_thumb_32_instr_ldrsb_immediate(r) NULL
 #define armv7_read_thumb_32_instr_ldrsb_literal(r) NULL
 #define armv7_read_thumb_32_instr_ldrsb_register(r) NULL
 #define armv7_read_thumb_32_instr_ldrsbt(r) NULL
+#define armv7_read_thumb_32_instr_ldrsh_immediate(r) NULL
+#define armv7_read_thumb_32_instr_ldrsh_literal(r) NULL
+#define armv7_read_thumb_32_instr_ldrsh_register(r) NULL
+#define armv7_read_thumb_32_instr_ldrsht(r) NULL
 #define armv7_read_thumb_32_instr_ldrt(r) NULL
 #define armv7_read_thumb_32_instr_lsl_register(r) NULL
 #define armv7_read_thumb_32_instr_lsr_register(r) NULL
+#define armv7_read_thumb_32_instr_mcr_mcr2(r) NULL
+#define armv7_read_thumb_32_instr_mcrr_mcrr2(r) NULL
+#define armv7_read_thumb_32_instr_mrc_mrc2(r) NULL
+#define armv7_read_thumb_32_instr_mrrc_mrrc2(r) NULL
 #define armv7_read_thumb_32_instr_mrs(r) NULL
 #define armv7_read_thumb_32_instr_mrs_banked_register(r) NULL
 #define armv7_read_thumb_32_instr_msr_banked_register(r) NULL
@@ -36,6 +57,8 @@
 #define armv7_read_thumb_32_instr_pkh(r) NULL
 #define armv7_read_thumb_32_instr_pld_immediate(r) NULL
 #define armv7_read_thumb_32_instr_pld_literal(r) NULL
+#define armv7_read_thumb_32_instr_pld_pldw_immediate(r) NULL
+#define armv7_read_thumb_32_instr_pld_pldw_register(r) NULL
 #define armv7_read_thumb_32_instr_pld_register(r) NULL
 #define armv7_read_thumb_32_instr_pli_immediate_literal(r) NULL
 #define armv7_read_thumb_32_instr_pli_register(r) NULL
@@ -48,7 +71,9 @@
 #define armv7_read_thumb_32_instr_rev16(r) NULL
 #define armv7_read_thumb_32_instr_revsh(r) NULL
 #define armv7_read_thumb_32_instr_rfe(r) NULL
+#define armv7_read_thumb_32_instr_ror_immediate(r) NULL
 #define armv7_read_thumb_32_instr_ror_register(r) NULL
+#define armv7_read_thumb_32_instr_rrx(r) NULL
 #define armv7_read_thumb_32_instr_sadd16(r) NULL
 #define armv7_read_thumb_32_instr_sadd8(r) NULL
 #define armv7_read_thumb_32_instr_sasx(r) NULL
@@ -89,9 +114,15 @@
 #define armv7_read_thumb_32_instr_ssax(r) NULL
 #define armv7_read_thumb_32_instr_ssub16(r) NULL
 #define armv7_read_thumb_32_instr_ssub8(r) NULL
+#define armv7_read_thumb_32_instr_stc_stc2(r) NULL
 #define armv7_read_thumb_32_instr_stmdb_stmfd(r) NULL
 #define armv7_read_thumb_32_instr_stm_stmia_stmea(r) NULL
 #define armv7_read_thumb_32_instr_strbt(r) NULL
+#define armv7_read_thumb_32_instr_strd_immediate(r) NULL
+#define armv7_read_thumb_32_instr_strex(r) NULL
+#define armv7_read_thumb_32_instr_strexb(r) NULL
+#define armv7_read_thumb_32_instr_strexd(r) NULL
+#define armv7_read_thumb_32_instr_strexh(r) NULL
 #define armv7_read_thumb_32_instr_strh_immediate_thumb(r) NULL
 #define armv7_read_thumb_32_instr_strh_register(r) NULL
 #define armv7_read_thumb_32_instr_strht(r) NULL
@@ -105,6 +136,7 @@
 #define armv7_read_thumb_32_instr_sxtb(r) NULL
 #define armv7_read_thumb_32_instr_sxtb16(r) NULL
 #define armv7_read_thumb_32_instr_sxth(r) NULL
+#define armv7_read_thumb_32_instr_tbb_tbh(r) NULL
 #define armv7_read_thumb_32_instr_uadd16(r) NULL
 #define armv7_read_thumb_32_instr_uadd8(r) NULL
 #define armv7_read_thumb_32_instr_uasx(r) NULL
diff --git a/src/arch/arm/v7/thumb_16.c b/src/arch/arm/v7/thumb_16.c
index c722f30..4697b3e 100644
--- a/src/arch/arm/v7/thumb_16.c
+++ b/src/arch/arm/v7/thumb_16.c
@@ -33,25 +33,25 @@
 
 
 
-/* Désassemble une instruction ARMv7 en mode Thumb 16 bits. */
+/* Désassemble une instruction ARMv7 liées au chapitre A6.2.1 */
 static GArchInstruction *process_armv7_thumb_16_shift_immediate_add_subtract_move_and_compare(uint16_t);
 
-/* Désassemble une instruction ARMv7 en mode Thumb 16 bits. */
+/* Désassemble une instruction ARMv7 liées au chapitre A6.2.2. */
 static GArchInstruction *process_armv7_thumb_16_data_processing(uint16_t);
 
-/* Désassemble une instruction ARMv7 en mode Thumb 16 bits. */
+/* Désassemble une instruction ARMv7 liées au chapitre A6.2.3. */
 static GArchInstruction *process_armv7_thumb_16_special_data_instructions_and_branch_and_exchange(uint16_t);
 
-/* Désassemble une instruction ARMv7 en mode Thumb 16 bits. */
+/* Désassemble une instruction ARMv7 liées au chapitre A6.2.4. */
 static GArchInstruction *process_armv7_thumb_16_load_store_single_data_item(uint16_t);
 
-/* Désassemble une instruction ARMv7 en mode Thumb 16 bits. */
+/* Désassemble une instruction ARMv7 liées au chapitre A6.2.5. */
 static GArchInstruction *process_armv7_thumb_16_miscellaneous_16_bit_instructions(uint16_t);
 
-/* Désassemble une instruction ARMv7 en mode Thumb 16 bits. */
+/* Désassemble une instruction ARMv7 liées au chapitre A6.2.5.b. */
 static GArchInstruction *process_armv7_thumb_16_miscellaneous_16_bit_instructions_if_then_and_hints(uint16_t);
 
-/* Désassemble une instruction ARMv7 en mode Thumb 16 bits. */
+/* Désassemble une instruction ARMv7 liées au chapitre A6.2.6. */
 static GArchInstruction *process_armv7_thumb_16_conditional_branch_and_supervisor_call(uint16_t);
 
 
@@ -60,7 +60,7 @@ static GArchInstruction *process_armv7_thumb_16_conditional_branch_and_superviso
 *                                                                             *
 *  Paramètres  : raw = donnée brute de 16 bits à désassembler.                *
 *                                                                             *
-*  Description : Désassemble une instruction ARMv7 en mode Thumb 16 bits.     *
+*  Description : Désassemble une instruction ARMv7 liées au chapitre A6.2.    *
 *                                                                             *
 *  Retour      : Instruction mise en place ou NULL en cas d'échec.            *
 *                                                                             *
@@ -133,7 +133,7 @@ GArchInstruction *process_armv7_thumb_16_instruction_set_encoding(uint16_t raw)
 *                                                                             *
 *  Paramètres  : raw = donnée brute de 16 bits à désassembler.                *
 *                                                                             *
-*  Description : Désassemble une instruction ARMv7 en mode Thumb 16 bits.     *
+*  Description : Désassemble une instruction ARMv7 liées au chapitre A6.2.1.  *
 *                                                                             *
 *  Retour      : Instruction mise en place ou NULL en cas d'échec.            *
 *                                                                             *
@@ -199,7 +199,7 @@ static GArchInstruction *process_armv7_thumb_16_shift_immediate_add_subtract_mov
 *                                                                             *
 *  Paramètres  : raw = donnée brute de 16 bits à désassembler.                *
 *                                                                             *
-*  Description : Désassemble une instruction ARMv7 en mode Thumb 16 bits.     *
+*  Description : Désassemble une instruction ARMv7 liées au chapitre A6.2.2.  *
 *                                                                             *
 *  Retour      : Instruction mise en place ou NULL en cas d'échec.            *
 *                                                                             *
@@ -300,7 +300,7 @@ static GArchInstruction *process_armv7_thumb_16_data_processing(uint16_t raw)
 *                                                                             *
 *  Paramètres  : raw = donnée brute de 16 bits à désassembler.                *
 *                                                                             *
-*  Description : Désassemble une instruction ARMv7 en mode Thumb 16 bits.     *
+*  Description : Désassemble une instruction ARMv7 liées au chapitre A6.2.3.  *
 *                                                                             *
 *  Retour      : Instruction mise en place ou NULL en cas d'échec.            *
 *                                                                             *
@@ -360,7 +360,7 @@ static GArchInstruction *process_armv7_thumb_16_special_data_instructions_and_br
 *                                                                             *
 *  Paramètres  : raw = donnée brute de 16 bits à désassembler.                *
 *                                                                             *
-*  Description : Désassemble une instruction ARMv7 en mode Thumb 16 bits.     *
+*  Description : Désassemble une instruction ARMv7 liées au chapitre A6.2.4.  *
 *                                                                             *
 *  Retour      : Instruction mise en place ou NULL en cas d'échec.            *
 *                                                                             *
@@ -471,7 +471,7 @@ static GArchInstruction *process_armv7_thumb_16_load_store_single_data_item(uint
 *                                                                             *
 *  Paramètres  : raw = donnée brute de 16 bits à désassembler.                *
 *                                                                             *
-*  Description : Désassemble une instruction ARMv7 en mode Thumb 16 bits.     *
+*  Description : Désassemble une instruction ARMv7 liées au chapitre A6.2.5.  *
 *                                                                             *
 *  Retour      : Instruction mise en place ou NULL en cas d'échec.            *
 *                                                                             *
@@ -561,7 +561,7 @@ static GArchInstruction *process_armv7_thumb_16_miscellaneous_16_bit_instruction
 *                                                                             *
 *  Paramètres  : raw = donnée brute de 16 bits à désassembler.                *
 *                                                                             *
-*  Description : Désassemble une instruction ARMv7 en mode Thumb 16 bits.     *
+*  Description : Désassemble une instruction ARMv7 liées au chapitre A6.2.5.b.*
 *                                                                             *
 *  Retour      : Instruction mise en place ou NULL en cas d'échec.            *
 *                                                                             *
@@ -588,7 +588,10 @@ static GArchInstruction *process_armv7_thumb_16_miscellaneous_16_bit_instruction
     opa = (raw >> 4) & b1111;
     opb = (raw >> 0) & b1111;
 
-    if (opb == b0000)
+    if (opb != b0000)
+        result = armv7_read_thumb_16_instr_it(raw);
+
+    else
         switch (opa)
         {
             case b0000:
@@ -613,9 +616,6 @@ static GArchInstruction *process_armv7_thumb_16_miscellaneous_16_bit_instruction
 
         }
 
-    else
-        result = armv7_read_thumb_16_instr_it(raw);
-
     return result;
 
 }
@@ -625,7 +625,7 @@ static GArchInstruction *process_armv7_thumb_16_miscellaneous_16_bit_instruction
 *                                                                             *
 *  Paramètres  : raw = donnée brute de 16 bits à désassembler.                *
 *                                                                             *
-*  Description : Désassemble une instruction ARMv7 en mode Thumb 16 bits.     *
+*  Description : Désassemble une instruction ARMv7 liées au chapitre A6.2.6.  *
 *                                                                             *
 *  Retour      : Instruction mise en place ou NULL en cas d'échec.            *
 *                                                                             *
diff --git a/src/arch/arm/v7/thumb_16.h b/src/arch/arm/v7/thumb_16.h
index bc50fd8..134a3aa 100644
--- a/src/arch/arm/v7/thumb_16.h
+++ b/src/arch/arm/v7/thumb_16.h
@@ -29,7 +29,7 @@
 
 
 
-/* Désassemble une instruction ARMv7 en mode Thumb 16 bits. */
+/* Désassemble une instruction ARMv7 liées au chapitre A6.2. */
 GArchInstruction *process_armv7_thumb_16_instruction_set_encoding(uint16_t);
 
 
diff --git a/src/arch/arm/v7/thumb_32.c b/src/arch/arm/v7/thumb_32.c
index 9d9de57..c1e3f3c 100644
--- a/src/arch/arm/v7/thumb_32.c
+++ b/src/arch/arm/v7/thumb_32.c
@@ -24,6 +24,7 @@
 #include "thumb_32.h"
 
 
+#include <assert.h>
 #include <stdint.h>
 
 
@@ -33,78 +34,65 @@
 
 
 
-
-
-
-/* Désassemble une instruction ARMv7 classique. */
+/* Désassemble une instruction ARMv7 liées au chapitre A6.3.1. */
 static GArchInstruction *process_armv7_thumb_32_data_processing_modified_immediate(uint32_t);
 
-/* Désassemble une instruction ARMv7 classique. */
+/* Désassemble une instruction ARMv7 liées au chapitre A6.3.3. */
 static GArchInstruction *process_armv7_thumb_32_data_processing_plain_binary_immediate(uint32_t);
 
-/* Désassemble une instruction ARMv7 classique. */
+/* Désassemble une instruction ARMv7 liées au chapitre A6.3.4. */
 static GArchInstruction *process_armv7_thumb_32_branches_and_miscellaneous_control(uint32_t);
 
-/* Désassemble une instruction ARMv7 classique. */
-static GArchInstruction *process_armv7_thumb_32_branches_and_miscellaneous_control_change_processor_state_and_hints(uint32_t);
+/* Désassemble une instruction ARMv7 liées au chapitre A6.3.4b. */
+static GArchInstruction *process_armv7_thumb_32_change_processor_state_and_hints(uint32_t);
 
-/* Désassemble une instruction ARMv7 classique. */
-static GArchInstruction *process_armv7_thumb_32_branches_and_miscellaneous_control_miscellaneous_control_instructions(uint32_t);
+/* Désassemble une instruction ARMv7 liées au chapitre A6.3.4t. */
+static GArchInstruction *process_armv7_thumb_32_miscellaneous_control_instructions(uint32_t);
 
-/* Désassemble une instruction ARMv7 classique. */
+/* Désassemble une instruction ARMv7 liées au chapitre A6.3.5. */
 static GArchInstruction *process_armv7_thumb_32_load_store_multiple(uint32_t);
 
+/* Désassemble une instruction ARMv7 liées au chapitre A6.3.6. */
+static GArchInstruction *process_armv7_thumb_32_load_store_dual_load_store_exclusive_table_branch(uint32_t);
 
-
-/* Désassemble une instruction ARMv7 classique. */
+/* Désassemble une instruction ARMv7 liées au chapitre A6.3.7. */
 static GArchInstruction *process_armv7_thumb_32_load_word(uint32_t);
 
+/* Désassemble une instruction ARMv7 liées au chapitre A6.3.8. */
+static GArchInstruction *process_armv7_thumb_32_load_halfword_memory_hints(uint32_t);
 
-
-
-/* Désassemble une instruction ARMv7 classique. */
+/* Désassemble une instruction ARMv7 liées au chapitre A6.3.9. */
 static GArchInstruction *process_armv7_thumb_32_load_byte_memory_hints(uint32_t);
 
-/* Désassemble une instruction ARMv7 classique. */
+/* Désassemble une instruction ARMv7 liées au chapitre A6.3.10. */
 static GArchInstruction *process_armv7_thumb_32_store_single_data_item(uint32_t);
 
-/* Désassemble une instruction ARMv7 classique. */
+/* Désassemble une instruction ARMv7 liées au chapitre A6.3.11. */
 static GArchInstruction *process_armv7_thumb_32_data_processing_shifted_register(uint32_t);
 
-/* Désassemble une instruction ARMv7 classique. */
+/* Désassemble une instruction ARMv7 liées au chapitre A6.3.11b. */
+static GArchInstruction *process_armv7_thumb_32_move_register_and_immediate_shifts(uint32_t);
+
+/* Désassemble une instruction ARMv7 liées au chapitre A6.3.12. */
 static GArchInstruction *process_armv7_thumb_32_data_processing_register(uint32_t);
 
-/* Désassemble une instruction ARMv7 classique. */
+/* Désassemble une instruction ARMv7 liées au chapitre A6.3.13. */
 static GArchInstruction *process_armv7_thumb_32_parallel_addition_and_subtraction_signed(uint32_t);
 
-/* Désassemble une instruction ARMv7 classique. */
+/* Désassemble une instruction ARMv7 liées au chapitre A6.3.14. */
 static GArchInstruction *process_armv7_thumb_32_parallel_addition_and_subtraction_unsigned(uint32_t);
 
-
-/* Désassemble une instruction ARMv7 classique. */
+/* Désassemble une instruction ARMv7 liées au chapitre A6.3.15. */
 static GArchInstruction *process_armv7_thumb_32_miscellaneous_operations(uint32_t);
 
-/* Désassemble une instruction ARMv7 classique. */
+/* Désassemble une instruction ARMv7 liées au chapitre A6.3.16. */
 static GArchInstruction *process_armv7_thumb_32_multiply_multiply_accumulate_and_absolute_difference(uint32_t);
 
-/* Désassemble une instruction ARMv7 classique. */
+/* Désassemble une instruction ARMv7 liées au chapitre A6.3.17. */
 static GArchInstruction *process_armv7_thumb_32_long_multiply_long_multiply_accumulate_and_divide(uint32_t);
 
-
-
-
-
-
-#define process_armv7_thumb_32_load_store_dual_load_store_exclusive_table_branch(r) NULL
-#define process_armv7_thumb_32_coprocessor_advanced_simd_and_floating_point_instructions(r) NULL
-
-#define process_armv7_thumb_32_load_halfword_memory_hints(r) NULL
-#define process_armv7_thumb_32_advanced_simd_element_or_structure_load_store_instructions(r) NULL
-#define process_armv7_thumb_32_move_register_and_immediate_shifts(r) NULL
-
-
-
-
+/* Désassemble une instruction ARMv7 liées au chapitre A6.3.18. */
+static GArchInstruction *process_armv7_thumb_32_coprocessor_advanced_simd_and_floating_point_instructions(uint32_t);
 
 
 
@@ -112,7 +100,7 @@ static GArchInstruction *process_armv7_thumb_32_long_multiply_long_multiply_accu
 *                                                                             *
 *  Paramètres  : raw = donnée brute de 32 bits à désassembler.                *
 *                                                                             *
-*  Description : Désassemble une instruction ARMv7 en mode Thumb 32 bits.     *
+*  Description : Désassemble une instruction ARMv7 liées au chapitre A6.3.    *
 *                                                                             *
 *  Retour      : Instruction mise en place ou NULL en cas d'échec.            *
 *                                                                             *
@@ -195,7 +183,9 @@ GArchInstruction *process_armv7_thumb_32_instruction_set_encoding(uint32_t raw)
             */
 
             else if ((op2 & b1110001) == b0010000)
-                result = process_armv7_thumb_32_advanced_simd_element_or_structure_load_store_instructions(raw);
+                /* Advanced SIMD element or structure load/store instructions on page A7-275 */
+                /*result = process_armv7_thumb_32_advanced_simd_element_or_structure_load_store_instructions(raw);*/
+                assert(false);
 
             else if ((op2 & b1110000) == b0100000)
                 result = process_armv7_thumb_32_data_processing_register(raw);
@@ -222,7 +212,7 @@ GArchInstruction *process_armv7_thumb_32_instruction_set_encoding(uint32_t raw)
 *                                                                             *
 *  Paramètres  : raw = donnée brute de 32 bits à désassembler.                *
 *                                                                             *
-*  Description : Désassemble une instruction ARMv7 classique.                 *
+*  Description : Désassemble une instruction ARMv7 liées au chapitre A6.3.1.  *
 *                                                                             *
 *  Retour      : Instruction mise en place ou NULL en cas d'échec.            *
 *                                                                             *
@@ -256,6 +246,7 @@ static GArchInstruction *process_armv7_thumb_32_data_processing_modified_immedia
 
             if (rds == b11111)
                 result = armv7_read_thumb_32_instr_tst_immediate(raw);
+
             else
                 result = armv7_read_thumb_32_instr_and_immediate(raw);
 
@@ -269,6 +260,7 @@ static GArchInstruction *process_armv7_thumb_32_data_processing_modified_immedia
 
             if (rn == b1111)
                 result = armv7_read_thumb_32_instr_mov_immediate(raw);
+
             else
                 result = armv7_read_thumb_32_instr_orr_immediate(raw);
 
@@ -278,6 +270,7 @@ static GArchInstruction *process_armv7_thumb_32_data_processing_modified_immedia
 
             if (rn == b1111)
                 result = armv7_read_thumb_32_instr_mvn_immediate(raw);
+
             else
                 result = armv7_read_thumb_32_instr_orn_immediate(raw);
 
@@ -287,6 +280,7 @@ static GArchInstruction *process_armv7_thumb_32_data_processing_modified_immedia
 
             if (rds == b11111)
                 result = armv7_read_thumb_32_instr_teq_immediate(raw);
+
             else
                 result = armv7_read_thumb_32_instr_eor_immediate(raw);
 
@@ -296,6 +290,7 @@ static GArchInstruction *process_armv7_thumb_32_data_processing_modified_immedia
 
             if (rds == b11111)
                 result = armv7_read_thumb_32_instr_cmn_immediate(raw);
+
             else
                 result = armv7_read_thumb_32_instr_add_immediate_thumb(raw);
 
@@ -313,6 +308,7 @@ static GArchInstruction *process_armv7_thumb_32_data_processing_modified_immedia
 
             if (rds == b11111)
                 result = armv7_read_thumb_32_instr_cmp_immediate(raw);
+
             else
                 result = armv7_read_thumb_32_instr_sub_immediate_thumb(raw);
 
@@ -333,7 +329,7 @@ static GArchInstruction *process_armv7_thumb_32_data_processing_modified_immedia
 *                                                                             *
 *  Paramètres  : raw = donnée brute de 32 bits à désassembler.                *
 *                                                                             *
-*  Description : Désassemble une instruction ARMv7 classique.                 *
+*  Description : Désassemble une instruction ARMv7 liées au chapitre A6.3.3.  *
 *                                                                             *
 *  Retour      : Instruction mise en place ou NULL en cas d'échec.            *
 *                                                                             *
@@ -365,6 +361,7 @@ static GArchInstruction *process_armv7_thumb_32_data_processing_plain_binary_imm
 
             if (rn == b1111)
                 result = armv7_read_thumb_32_instr_adr(raw);
+
             else
                 result = armv7_read_thumb_32_instr_add_immediate_thumb(raw);
 
@@ -378,6 +375,7 @@ static GArchInstruction *process_armv7_thumb_32_data_processing_plain_binary_imm
 
             if (rn == b11111)
                 result = armv7_read_thumb_32_instr_adr(raw);
+
             else
                 result = armv7_read_thumb_32_instr_sub_immediate_thumb(raw);
 
@@ -392,10 +390,13 @@ static GArchInstruction *process_armv7_thumb_32_data_processing_plain_binary_imm
             break;
 
         case b10010:
+
             if ((raw & 0x000070c0) != 0)
                 result = armv7_read_thumb_32_instr_ssat(raw);
+
             else
                 result = armv7_read_thumb_32_instr_ssat16(raw);
+
             break;
 
         case b10100:
@@ -406,6 +407,7 @@ static GArchInstruction *process_armv7_thumb_32_data_processing_plain_binary_imm
 
             if (rn == b11111)
                 result = armv7_read_thumb_32_instr_bfc(raw);
+
             else
                 result = armv7_read_thumb_32_instr_bfi(raw);
 
@@ -416,10 +418,13 @@ static GArchInstruction *process_armv7_thumb_32_data_processing_plain_binary_imm
             break;
 
         case b11010:
+
             if ((raw & 0x000070c0) != 0)
                 result = armv7_read_thumb_32_instr_usat(raw);
+
             else
                 result = armv7_read_thumb_32_instr_usat16(raw);
+
             break;
 
         case b11100:
@@ -437,7 +442,7 @@ static GArchInstruction *process_armv7_thumb_32_data_processing_plain_binary_imm
 *                                                                             *
 *  Paramètres  : raw = donnée brute de 32 bits à désassembler.                *
 *                                                                             *
-*  Description : Désassemble une instruction ARMv7 classique.                 *
+*  Description : Désassemble une instruction ARMv7 liées au chapitre A6.3.4.  *
 *                                                                             *
 *  Retour      : Instruction mise en place ou NULL en cas d'échec.            *
 *                                                                             *
@@ -494,10 +499,10 @@ static GArchInstruction *process_armv7_thumb_32_branches_and_miscellaneous_contr
             result = armv7_read_thumb_32_instr_b_msr_register(raw);
 
         else if (op == b0111010)
-            result = process_armv7_thumb_32_branches_and_miscellaneous_control_change_processor_state_and_hints(raw);
+            result = process_armv7_thumb_32_change_processor_state_and_hints(raw);
 
         else if (op == b0111011)
-            result = process_armv7_thumb_32_branches_and_miscellaneous_control_miscellaneous_control_instructions(raw);
+            result = process_armv7_thumb_32_miscellaneous_control_instructions(raw);
 
         else if (op == b0111100)
             result = armv7_read_thumb_32_instr_bxj(raw);
@@ -542,13 +547,13 @@ static GArchInstruction *process_armv7_thumb_32_branches_and_miscellaneous_contr
 *                                                                             *
 *  Description : Désassemble une instruction ARMv7 classique.                 *
 *                                                                             *
-*  Retour      : Instruction mise en place ou NULL en cas d'échec.            *
+*  Retour      : Désassemble une instruction ARMv7 liées au chapitre A6.3.4b. *
 *                                                                             *
 *  Remarques   : -                                                            *
 *                                                                             *
 ******************************************************************************/
 
-static GArchInstruction *process_armv7_thumb_32_branches_and_miscellaneous_control_change_processor_state_and_hints(uint32_t raw)
+static GArchInstruction *process_armv7_thumb_32_change_processor_state_and_hints(uint32_t raw)
 {
     GArchInstruction *result;               /* Instruction à renvoyer      */
     uint32_t op1;                           /* Champ 'op1' à retrouver     */
@@ -601,7 +606,7 @@ static GArchInstruction *process_armv7_thumb_32_branches_and_miscellaneous_contr
 *                                                                             *
 *  Paramètres  : raw = donnée brute de 32 bits à désassembler.                *
 *                                                                             *
-*  Description : Désassemble une instruction ARMv7 classique.                 *
+*  Description : Désassemble une instruction ARMv7 liées au chapitre A6.3.4t. *
 *                                                                             *
 *  Retour      : Instruction mise en place ou NULL en cas d'échec.            *
 *                                                                             *
@@ -609,7 +614,7 @@ static GArchInstruction *process_armv7_thumb_32_branches_and_miscellaneous_contr
 *                                                                             *
 ******************************************************************************/
 
-static GArchInstruction *process_armv7_thumb_32_branches_and_miscellaneous_control_miscellaneous_control_instructions(uint32_t raw)
+static GArchInstruction *process_armv7_thumb_32_miscellaneous_control_instructions(uint32_t raw)
 {
     GArchInstruction *result;               /* Instruction à renvoyer      */
     uint32_t op;                            /* Champ 'op' à retrouver      */
@@ -663,7 +668,7 @@ static GArchInstruction *process_armv7_thumb_32_branches_and_miscellaneous_contr
 *                                                                             *
 *  Paramètres  : raw = donnée brute de 32 bits à désassembler.                *
 *                                                                             *
-*  Description : Désassemble une instruction ARMv7 classique.                 *
+*  Description : Désassemble une instruction ARMv7 liées au chapitre A6.3.5.  *
 *                                                                             *
 *  Retour      : Instruction mise en place ou NULL en cas d'échec.            *
 *                                                                             *
@@ -697,6 +702,7 @@ static GArchInstruction *process_armv7_thumb_32_load_store_multiple(uint32_t raw
 
             if (l == b0)
                 result = armv7_read_thumb_32_instr_srs_thumb(raw);
+
             else
                 result = armv7_read_thumb_32_instr_rfe(raw);
 
@@ -711,8 +717,10 @@ static GArchInstruction *process_armv7_thumb_32_load_store_multiple(uint32_t raw
             {
                 if (wrn == b11101)
                     result = armv7_read_thumb_32_instr_pop_thumb(raw);
+
                 else
                     result = armv7_read_thumb_32_instr_ldm_ldmia_ldmfd_thumb(raw);
+
             }
 
             break;
@@ -723,8 +731,10 @@ static GArchInstruction *process_armv7_thumb_32_load_store_multiple(uint32_t raw
             {
                 if (wrn == b11101)
                     result = armv7_read_thumb_32_instr_push(raw);
+
                 else
                     result = armv7_read_thumb_32_instr_stmdb_stmfd(raw);
+
             }
 
             else
@@ -736,6 +746,7 @@ static GArchInstruction *process_armv7_thumb_32_load_store_multiple(uint32_t raw
 
             if (l == b0)
                 result = armv7_read_thumb_32_instr_srs_thumb(raw);
+
             else
                 result = armv7_read_thumb_32_instr_rfe(raw);
 
@@ -748,21 +759,124 @@ static GArchInstruction *process_armv7_thumb_32_load_store_multiple(uint32_t raw
 }
 
 
+/******************************************************************************
+*                                                                             *
+*  Paramètres  : raw = donnée brute de 32 bits à désassembler.                *
+*                                                                             *
+*  Description : Désassemble une instruction ARMv7 liées au chapitre A6.3.6.  *
+*                                                                             *
+*  Retour      : Instruction mise en place ou NULL en cas d'échec.            *
+*                                                                             *
+*  Remarques   : -                                                            *
+*                                                                             *
+******************************************************************************/
+
+static GArchInstruction *process_armv7_thumb_32_load_store_dual_load_store_exclusive_table_branch(uint32_t raw)
+{
+    GArchInstruction *result;               /* Instruction à renvoyer      */
+    uint32_t op1;                           /* Champ 'op1' à retrouver     */
+    uint32_t op2;                           /* Champ 'op2' à retrouver     */
+    uint32_t rn;                            /* Champ 'rn' à retrouver      */
+    uint32_t op3;                           /* Champ 'op3' à retrouver     */
+
+    /**
+     * Suit les directives de :
+     * § A6.3.6 Load/store dual, load/store exclusive, table branch
+     */
+
+    if ((raw & 0xfe400000) != 0xe8400000) return NULL;
+
+    result = NULL;
+
+    op1 = (raw >> 23) & 0x3;
+    op2 = (raw >> 20) & 0x3;
+    rn = (raw >> 16) & 0xf;
+    op3 = (raw >> 4) & 0xf;
+
+    if (op1 == b00 && op2 == b00)
+        result = armv7_read_thumb_32_instr_strex(raw);
+
+    else if (op1 == b00 && op2 == b01)
+        result = armv7_read_thumb_32_instr_ldrex(raw);
+
+    else if ((op1 & b10) == b00 && op2 == b10)
+        result = armv7_read_thumb_32_instr_strd_immediate(raw);
+
+    else if ((op1 & b10) == b10 && (op2 & b01) == b00)
+        result = armv7_read_thumb_32_instr_strd_immediate(raw);
+
+    else if ((op1 & b10) == b00 && op2 == b11)
+    {
+        if (rn != b1111)
+            result = armv7_read_thumb_32_instr_ldrd_immediate(raw);
+
+        else/* if (rn == b1111)*/
+            result = armv7_read_thumb_32_instr_ldrd_literal(raw);
+
+    }
+
+    else if ((op1 & b10) == b10 && (op2 & b01) == b01)
+    {
+        if (rn != b1111)
+            result = armv7_read_thumb_32_instr_ldrd_immediate(raw);
+
+        else/* if (rn == b1111)*/
+            result = armv7_read_thumb_32_instr_ldrd_literal(raw);
+
+    }
+
+    else if (op1 == b01 && op2 == b00)
+        switch (op3)
+        {
+            case b0100:
+                result = armv7_read_thumb_32_instr_strexb(raw);
+                break;
+
+            case b0101:
+                result = armv7_read_thumb_32_instr_strexh(raw);
+                break;
 
+            case b0111:
+                result = armv7_read_thumb_32_instr_strexd(raw);
+                break;
 
+        }
 
+    else if (op1 == b01 && op2 == b01)
+        switch (op3)
+        {
+            case b0000:
+                result = armv7_read_thumb_32_instr_tbb_tbh(raw);
+                break;
 
+            case b0001:
+                result = armv7_read_thumb_32_instr_tbb_tbh(raw);
+                break;
 
+            case b0100:
+                result = armv7_read_thumb_32_instr_ldrexb(raw);
+                break;
 
+            case b0101:
+                result = armv7_read_thumb_32_instr_ldrexh(raw);
+                break;
 
+            case b0111:
+                result = armv7_read_thumb_32_instr_ldrexd(raw);
+                break;
 
+        }
+
+    return result;
+
+}
 
 
 /******************************************************************************
 *                                                                             *
 *  Paramètres  : raw = donnée brute de 32 bits à désassembler.                *
 *                                                                             *
-*  Description : Désassemble une instruction ARMv7 classique.                 *
+*  Description : Désassemble une instruction ARMv7 liées au chapitre A6.3.7.  *
 *                                                                             *
 *  Retour      : Instruction mise en place ou NULL en cas d'échec.            *
 *                                                                             *
@@ -823,22 +937,146 @@ static GArchInstruction *process_armv7_thumb_32_load_word(uint32_t raw)
 }
 
 
+/******************************************************************************
+*                                                                             *
+*  Paramètres  : raw = donnée brute de 32 bits à désassembler.                *
+*                                                                             *
+*  Description : Désassemble une instruction ARMv7 liées au chapitre A6.3.8.  *
+*                                                                             *
+*  Retour      : Instruction mise en place ou NULL en cas d'échec.            *
+*                                                                             *
+*  Remarques   : -                                                            *
+*                                                                             *
+******************************************************************************/
+
+static GArchInstruction *process_armv7_thumb_32_load_halfword_memory_hints(uint32_t raw)
+{
+    GArchInstruction *result;               /* Instruction à renvoyer      */
+    uint32_t op1;                           /* Champ 'op1' à retrouver     */
+    uint32_t rn;                            /* Champ 'rn' à retrouver      */
+    uint32_t rt;                            /* Champ 'rt' à retrouver      */
+    uint32_t op2;                           /* Champ 'op2' à retrouver     */
+
+    /**
+     * Suit les directives de :
+     * § A6.3.8 Load halfword, memory hints
+     */
+
+    if ((raw & 0xfe700000) != 0xf8300000) return NULL;
+
+    result = NULL;
+
+    op1 = (raw >> 23) & 0x3;
+    rn = (raw >> 16) & 0xf;
+    rt = (raw >> 12) & 0xf;
+    op2 = (raw >> 6) & 0x3f;
+
+    if (rn == b1111)
+    {
+        if ((op1 & b10) == b00)
+        {
+            if (rt != b1111)
+                result = armv7_read_thumb_32_instr_ldrh_literal(raw);
+
+            else/* if (rt == b1111)*/
+                result = armv7_read_thumb_32_instr_pld_literal(raw);
+
+        }
+
+        else/* if ((op1 & b10) == b10)*/
+        {
+            if (rt != b1111)
+                result = armv7_read_thumb_32_instr_ldrsh_literal(raw);
+
+            else/* if (rt == b1111)*/
+                /* Unallocated memory hint (treat as NOP) */
+                assert(false);
+
+        }
+
+    }
+
+    else/* if (rn != b1111)*/
+    {
+        if (op1 == b00)
+        {
+            if ((op2 & b100100) == b100100)
+                result = armv7_read_thumb_32_instr_ldrh_immediate_thumb(raw);
 
+            else if ((op2 & b111100) == b110000 && rt != b1111)
+                result = armv7_read_thumb_32_instr_ldrh_immediate_thumb(raw);
+
+            else if (op2 == b000000 && rt != b1111)
+                result = armv7_read_thumb_32_instr_ldrh_register(raw);
+
+            else if ((op2 & b111100) == b111000)
+                result = armv7_read_thumb_32_instr_ldrht(raw);
 
+            else if (op2 == b000000 && rt == b1111)
+                result = armv7_read_thumb_32_instr_pld_pldw_register(raw);
 
+            else if ((op2 & b111100) == b110000 && rt == b1111)
+                result = armv7_read_thumb_32_instr_pld_pldw_immediate(raw);
 
+        }
 
+        else if (op1 == b01)
+        {
+            if (rt != b1111)
+                result = armv7_read_thumb_32_instr_ldrh_immediate_thumb(raw);
 
+            else/* if (rt == b1111)*/
+                result = armv7_read_thumb_32_instr_pld_pldw_immediate(raw);
 
+        }
+
+        else if (op1 == b10)
+        {
+            if ((op2 & b100100) == b100100)
+                result = armv7_read_thumb_32_instr_ldrsh_immediate(raw);
+
+            else if ((op2 & b111100) == b110000 && rt != b1111)
+                result = armv7_read_thumb_32_instr_ldrsh_immediate(raw);
+
+            else if (op2 == b000000 && rt != b1111)
+                result = armv7_read_thumb_32_instr_ldrsh_register(raw);
+
+            else if ((op2 & b111100) == b111000)
+                result = armv7_read_thumb_32_instr_ldrsht(raw);
 
+            else if (op2 == b000000 && rt == b1111)
+                /* Unallocated memory hint (treat as NOP) */
+                assert(false);
 
+            else if ((op2 & b111100) == b110000 && rt == b1111)
+                /* Unallocated memory hint (treat as NOP) */
+                assert(false);
+
+        }
+
+        else if (op1 == b11)
+        {
+            if (rt != b1111)
+                result = armv7_read_thumb_32_instr_ldrsh_immediate(raw);
+
+            else/* if (rt == b1111)*/
+                /* Unallocated memory hint (treat as NOP) */
+                assert(false);
+
+        }
+
+    }
+
+    return result;
+
+}
 
 
 /******************************************************************************
 *                                                                             *
 *  Paramètres  : raw = donnée brute de 32 bits à désassembler.                *
 *                                                                             *
-*  Description : Désassemble une instruction ARMv7 classique.                 *
+*  Description : Désassemble une instruction ARMv7 liées au chapitre A6.3.9.  *
 *                                                                             *
 *  Retour      : Instruction mise en place ou NULL en cas d'échec.            *
 *                                                                             *
@@ -872,16 +1110,20 @@ static GArchInstruction *process_armv7_thumb_32_load_byte_memory_hints(uint32_t
     {
         if (rt != b1111)
             result = armv7_read_thumb_32_instr_ldrb_register(raw);
+
         else /*if (rt == b1111) */
             result = armv7_read_thumb_32_instr_pld_register(raw);
+
     }
 
     else if ((op1 & b10) == b00 && rn == b1111)
     {
         if (rt != b1111)
             result = armv7_read_thumb_32_instr_ldrb_literal(raw);
+
         else /*if (rt == b1111) */
             result = armv7_read_thumb_32_instr_pld_literal(raw);
+
     }
 
     else if (op1 == b00 && (op2 & b100100) == b100100 && rn != b1111)
@@ -891,8 +1133,10 @@ static GArchInstruction *process_armv7_thumb_32_load_byte_memory_hints(uint32_t
     {
         if (rt != b1111)
             result = armv7_read_thumb_32_instr_ldrb_immediate_thumb(raw);
+
         else /*if (rt == b1111) */
             result = armv7_read_thumb_32_instr_pld_immediate(raw);
+
     }
 
     else if (op1 == b00 && (op2 & b111100) == b111000 && rn != b1111)
@@ -902,8 +1146,10 @@ static GArchInstruction *process_armv7_thumb_32_load_byte_memory_hints(uint32_t
     {
         if (rt != b1111)
             result = armv7_read_thumb_32_instr_ldrb_immediate_thumb(raw);
+
         else /*if (rt == b1111) */
             result = armv7_read_thumb_32_instr_pld_immediate(raw);
+
     }
 
     if (op1 == b10 && op2 == b000000 && rn != b1111)
@@ -918,8 +1164,10 @@ static GArchInstruction *process_armv7_thumb_32_load_byte_memory_hints(uint32_t
     {
         if (rt != b1111)
             result = armv7_read_thumb_32_instr_ldrsb_literal(raw);
+
         else /*if (rt == b1111) */
             result = armv7_read_thumb_32_instr_pli_immediate_literal(raw);
+
     }
 
     else if (op1 == b10 && (op2 & b100100) == b100100 && rn != b1111)
@@ -929,8 +1177,10 @@ static GArchInstruction *process_armv7_thumb_32_load_byte_memory_hints(uint32_t
     {
         if (rt != b1111)
             result = armv7_read_thumb_32_instr_ldrsb_immediate(raw);
+
         else /*if (rt == b1111) */
             result = armv7_read_thumb_32_instr_pli_immediate_literal(raw);
+
     }
 
     else if (op1 == b10 && (op2 & b111100) == b111000 && rn != b1111)
@@ -940,8 +1190,10 @@ static GArchInstruction *process_armv7_thumb_32_load_byte_memory_hints(uint32_t
     {
         if (rt != b1111)
             result = armv7_read_thumb_32_instr_ldrsb_immediate(raw);
+
         else /*if (rt == b1111) */
             result = armv7_read_thumb_32_instr_pli_immediate_literal(raw);
+
     }
 
     return result;
@@ -953,7 +1205,7 @@ static GArchInstruction *process_armv7_thumb_32_load_byte_memory_hints(uint32_t
 *                                                                             *
 *  Paramètres  : raw = donnée brute de 32 bits à désassembler.                *
 *                                                                             *
-*  Description : Désassemble une instruction ARMv7 classique.                 *
+*  Description : Désassemble une instruction ARMv7 liées au chapitre A6.3.10. *
 *                                                                             *
 *  Retour      : Instruction mise en place ou NULL en cas d'échec.            *
 *                                                                             *
@@ -1052,7 +1304,7 @@ static GArchInstruction *process_armv7_thumb_32_store_single_data_item(uint32_t
 *                                                                             *
 *  Paramètres  : raw = donnée brute de 32 bits à désassembler.                *
 *                                                                             *
-*  Description : Désassemble une instruction ARMv7 classique.                 *
+*  Description : Désassemble une instruction ARMv7 liées au chapitre A6.3.11. *
 *                                                                             *
 *  Retour      : Instruction mise en place ou NULL en cas d'échec.            *
 *                                                                             *
@@ -1086,6 +1338,7 @@ static GArchInstruction *process_armv7_thumb_32_data_processing_shifted_register
 
             if (rds == b11111)
                 result = armv7_read_thumb_32_instr_tst_register(raw);
+
             else
                 result = armv7_read_thumb_32_instr_and_register(raw);
 
@@ -1099,6 +1352,7 @@ static GArchInstruction *process_armv7_thumb_32_data_processing_shifted_register
 
             if (rn == b11111)
                 result = process_armv7_thumb_32_move_register_and_immediate_shifts(raw);
+
             else
                 result = armv7_read_thumb_32_instr_orr_register(raw);
 
@@ -1108,6 +1362,7 @@ static GArchInstruction *process_armv7_thumb_32_data_processing_shifted_register
 
             if (rn == b11111)
                 result = armv7_read_thumb_32_instr_mvn_register(raw);
+
             else
                 result = armv7_read_thumb_32_instr_orn_register(raw);
 
@@ -1117,6 +1372,7 @@ static GArchInstruction *process_armv7_thumb_32_data_processing_shifted_register
 
             if (rds == b11111)
                 result = armv7_read_thumb_32_instr_teq_register(raw);
+
             else
                 result = armv7_read_thumb_32_instr_eor_register(raw);
 
@@ -1130,6 +1386,7 @@ static GArchInstruction *process_armv7_thumb_32_data_processing_shifted_register
 
             if (rds == b11111)
                 result = armv7_read_thumb_32_instr_cmn_register(raw);
+
             else
                 result = armv7_read_thumb_32_instr_add_register_thumb(raw);
 
@@ -1147,6 +1404,7 @@ static GArchInstruction *process_armv7_thumb_32_data_processing_shifted_register
 
             if (rds == b11111)
                 result = armv7_read_thumb_32_instr_cmp_register(raw);
+
             else
                 result = armv7_read_thumb_32_instr_sub_register_thumb(raw);
 
@@ -1167,7 +1425,75 @@ static GArchInstruction *process_armv7_thumb_32_data_processing_shifted_register
 *                                                                             *
 *  Paramètres  : raw = donnée brute de 32 bits à désassembler.                *
 *                                                                             *
-*  Description : Désassemble une instruction ARMv7 classique.                 *
+*  Description : Désassemble une instruction ARMv7 liées au chapitre A6.3.11b.*
+*                                                                             *
+*  Retour      : Instruction mise en place ou NULL en cas d'échec.            *
+*                                                                             *
+*  Remarques   : -                                                            *
+*                                                                             *
+******************************************************************************/
+
+static GArchInstruction *process_armv7_thumb_32_move_register_and_immediate_shifts(uint32_t raw)
+{
+    GArchInstruction *result;               /* Instruction à renvoyer      */
+    uint32_t imm5;                          /* Champs 'imm[32]' à retrouver*/
+    uint32_t type;                          /* Champ 'type' à retrouver    */
+
+    /**
+     * Suit les directives de :
+     * § A6.3.11 Data-processing (shifted register)
+     *    |-> Move register and immediate shifts
+     */
+
+    if ((raw & 0xffef0000) != 0xea4f0000) return NULL;
+
+    result = NULL;
+
+    imm5 = (((raw >> 12) & 0x7) << 2) | ((raw >> 6) & 0x3);
+    type = (raw >> 4) & 0x3;
+
+    switch (type)
+    {
+        case b00:
+
+            if (imm5 == b00000)
+                result = armv7_read_thumb_32_instr_mov_register_thumb(raw);
+
+            else/* if (imm5 != b00000)*/
+                result = armv7_read_thumb_32_instr_lsl_immediate(raw);
+
+            break;
+
+        case b01:
+            result = armv7_read_thumb_32_instr_lsr_immediate(raw);
+            break;
+
+        case b10:
+            result = armv7_read_thumb_32_instr_asr_immediate(raw);
+            break;
+
+        case b11:
+
+            if (imm5 == b00000)
+                result = armv7_read_thumb_32_instr_rrx(raw);
+
+            else/* if (imm5 != b00000)*/
+                result = armv7_read_thumb_32_instr_ror_immediate(raw);
+
+            break;
+
+    }
+
+    return result;
+
+}
+
+
+/******************************************************************************
+*                                                                             *
+*  Paramètres  : raw = donnée brute de 32 bits à désassembler.                *
+*                                                                             *
+*  Description : Désassemble une instruction ARMv7 liées au chapitre A6.3.12. *
 *                                                                             *
 *  Retour      : Instruction mise en place ou NULL en cas d'échec.            *
 *                                                                             *
@@ -1211,48 +1537,60 @@ static GArchInstruction *process_armv7_thumb_32_data_processing_register(uint32_
     {
         if (rn == b1111)
             result = armv7_read_thumb_32_instr_sxth(raw);
+
         else
             result = armv7_read_thumb_32_instr_sxtah(raw);
+
     }
 
     else if (op1 == b0001 && (op2 & b1000) == b1000)
     {
         if (rn == b1111)
             result = armv7_read_thumb_32_instr_uxth(raw);
+
         else
             result = armv7_read_thumb_32_instr_uxtah(raw);
+
     }
 
     else if (op1 == b0010 && (op2 & b1000) == b1000)
     {
         if (rn == b1111)
             result = armv7_read_thumb_32_instr_sxtb16(raw);
+
         else
             result = armv7_read_thumb_32_instr_sxtab16(raw);
+
     }
 
     else if (op1 == b0011 && (op2 & b1000) == b1000)
     {
         if (rn == b1111)
             result = armv7_read_thumb_32_instr_uxtb16(raw);
+
         else
             result = armv7_read_thumb_32_instr_uxtab16(raw);
+
     }
 
     else if (op1 == b0100 && (op2 & b1000) == b1000)
     {
         if (rn == b1111)
             result = armv7_read_thumb_32_instr_sxtb(raw);
+
         else
             result = armv7_read_thumb_32_instr_sxtab(raw);
+
     }
 
     else if (op1 == b0101 && (op2 & b1000) == b1000)
     {
         if (rn == b1111)
             result = armv7_read_thumb_32_instr_uxtb(raw);
+
         else
             result = armv7_read_thumb_32_instr_uxtab(raw);
+
     }
 
     else if ((op1 & b1000) == b1000 && (op2 & b1100) == b0000)
@@ -1273,7 +1611,7 @@ static GArchInstruction *process_armv7_thumb_32_data_processing_register(uint32_
 *                                                                             *
 *  Paramètres  : raw = donnée brute de 32 bits à désassembler.                *
 *                                                                             *
-*  Description : Désassemble une instruction ARMv7 classique.                 *
+*  Description : Désassemble une instruction ARMv7 liées au chapitre A6.3.13. *
 *                                                                             *
 *  Retour      : Instruction mise en place ou NULL en cas d'échec.            *
 *                                                                             *
@@ -1307,21 +1645,27 @@ static GArchInstruction *process_armv7_thumb_32_parallel_addition_and_subtractio
                 case b001:
                     result = armv7_read_thumb_32_instr_sadd16(raw);
                     break;
+
                 case b010:
                     result = armv7_read_thumb_32_instr_sasx(raw);
                     break;
+
                 case b110:
                     result = armv7_read_thumb_32_instr_ssax(raw);
                     break;
+
                 case b101:
                     result = armv7_read_thumb_32_instr_ssub16(raw);
                     break;
+
                 case b000:
                     result = armv7_read_thumb_32_instr_sadd8(raw);
                     break;
+
                 case b100:
                     result = armv7_read_thumb_32_instr_ssub8(raw);
                     break;
+
             }
             break;
 
@@ -1331,21 +1675,27 @@ static GArchInstruction *process_armv7_thumb_32_parallel_addition_and_subtractio
                 case b001:
                     result = armv7_read_thumb_32_instr_sqadd16(raw);
                     break;
+
                 case b010:
                     result = armv7_read_thumb_32_instr_sqasx(raw);
                     break;
+
                 case b110:
                     result = armv7_read_thumb_32_instr_sqsax(raw);
                     break;
+
                 case b101:
                     result = armv7_read_thumb_32_instr_sqsub16(raw);
                     break;
+
                 case b000:
                     result = armv7_read_thumb_32_instr_sqadd8(raw);
                     break;
+
                 case b100:
                     result = armv7_read_thumb_32_instr_sqsub8(raw);
                     break;
+
             }
             break;
 
@@ -1355,21 +1705,27 @@ static GArchInstruction *process_armv7_thumb_32_parallel_addition_and_subtractio
                 case b001:
                     result = armv7_read_thumb_32_instr_shadd16(raw);
                     break;
+
                 case b010:
                     result = armv7_read_thumb_32_instr_shasx(raw);
                     break;
+
                 case b110:
                     result = armv7_read_thumb_32_instr_shsax(raw);
                     break;
+
                 case b101:
                     result = armv7_read_thumb_32_instr_shsub16(raw);
                     break;
+
                 case b000:
                     result = armv7_read_thumb_32_instr_shadd8(raw);
                     break;
+
                 case b100:
                     result = armv7_read_thumb_32_instr_shsub8(raw);
                     break;
+
             }
             break;
 
@@ -1384,7 +1740,7 @@ static GArchInstruction *process_armv7_thumb_32_parallel_addition_and_subtractio
 *                                                                             *
 *  Paramètres  : raw = donnée brute de 32 bits à désassembler.                *
 *                                                                             *
-*  Description : Désassemble une instruction ARMv7 classique.                 *
+*  Description : Désassemble une instruction ARMv7 liées au chapitre A6.3.14. *
 *                                                                             *
 *  Retour      : Instruction mise en place ou NULL en cas d'échec.            *
 *                                                                             *
@@ -1418,21 +1774,27 @@ static GArchInstruction *process_armv7_thumb_32_parallel_addition_and_subtractio
                 case b001:
                     result = armv7_read_thumb_32_instr_uadd16(raw);
                     break;
+
                 case b010:
                     result = armv7_read_thumb_32_instr_uasx(raw);
                     break;
+
                 case b110:
                     result = armv7_read_thumb_32_instr_usax(raw);
                     break;
+
                 case b101:
                     result = armv7_read_thumb_32_instr_usub16(raw);
                     break;
+
                 case b000:
                     result = armv7_read_thumb_32_instr_uadd8(raw);
                     break;
+
                 case b100:
                     result = armv7_read_thumb_32_instr_usub8(raw);
                     break;
+
             }
             break;
 
@@ -1442,21 +1804,27 @@ static GArchInstruction *process_armv7_thumb_32_parallel_addition_and_subtractio
                 case b001:
                     result = armv7_read_thumb_32_instr_uqadd16(raw);
                     break;
+
                 case b010:
                     result = armv7_read_thumb_32_instr_uqasx(raw);
                     break;
+
                 case b110:
                     result = armv7_read_thumb_32_instr_uqsax(raw);
                     break;
+
                 case b101:
                     result = armv7_read_thumb_32_instr_uqsub16(raw);
                     break;
+
                 case b000:
                     result = armv7_read_thumb_32_instr_uqadd8(raw);
                     break;
+
                 case b100:
                     result = armv7_read_thumb_32_instr_uqsub8(raw);
                     break;
+
             }
             break;
 
@@ -1466,21 +1834,27 @@ static GArchInstruction *process_armv7_thumb_32_parallel_addition_and_subtractio
                 case b001:
                     result = armv7_read_thumb_32_instr_uhadd16(raw);
                     break;
+
                 case b010:
                     result = armv7_read_thumb_32_instr_uhasx(raw);
                     break;
+
                 case b110:
                     result = armv7_read_thumb_32_instr_uhsax(raw);
                     break;
+
                 case b101:
                     result = armv7_read_thumb_32_instr_uhsub16(raw);
                     break;
+
                 case b000:
                     result = armv7_read_thumb_32_instr_uhadd8(raw);
                     break;
+
                 case b100:
                     result = armv7_read_thumb_32_instr_uhsub8(raw);
                     break;
+
             }
             break;
 
@@ -1495,7 +1869,7 @@ static GArchInstruction *process_armv7_thumb_32_parallel_addition_and_subtractio
 *                                                                             *
 *  Paramètres  : raw = donnée brute de 32 bits à désassembler.                *
 *                                                                             *
-*  Description : Désassemble une instruction ARMv7 classique.                 *
+*  Description : Désassemble une instruction ARMv7 liées au chapitre A6.3.15. *
 *                                                                             *
 *  Retour      : Instruction mise en place ou NULL en cas d'échec.            *
 *                                                                             *
@@ -1529,15 +1903,19 @@ static GArchInstruction *process_armv7_thumb_32_miscellaneous_operations(uint32_
                 case b00:
                     result = armv7_read_thumb_32_instr_qadd(raw);
                     break;
+
                 case b01:
                     result = armv7_read_thumb_32_instr_qdadd(raw);
                     break;
+
                 case b10:
                     result = armv7_read_thumb_32_instr_qsub(raw);
                     break;
+
                 case b11:
                     result = armv7_read_thumb_32_instr_qdsub(raw);
                     break;
+
             }
             break;
 
@@ -1547,15 +1925,19 @@ static GArchInstruction *process_armv7_thumb_32_miscellaneous_operations(uint32_
                 case b00:
                     result = armv7_read_thumb_32_instr_rev(raw);
                     break;
+
                 case b01:
                     result = armv7_read_thumb_32_instr_rev16(raw);
                     break;
+
                 case b10:
                     result = armv7_read_thumb_32_instr_rbit(raw);
                     break;
+
                 case b11:
                     result = armv7_read_thumb_32_instr_revsh(raw);
                     break;
+
             }
             break;
 
@@ -1580,7 +1962,7 @@ static GArchInstruction *process_armv7_thumb_32_miscellaneous_operations(uint32_
 *                                                                             *
 *  Paramètres  : raw = donnée brute de 32 bits à désassembler.                *
 *                                                                             *
-*  Description : Désassemble une instruction ARMv7 classique.                 *
+*  Description : Désassemble une instruction ARMv7 liées au chapitre A6.3.16. *
 *                                                                             *
 *  Retour      : Instruction mise en place ou NULL en cas d'échec.            *
 *                                                                             *
@@ -1616,8 +1998,10 @@ static GArchInstruction *process_armv7_thumb_32_multiply_multiply_accumulate_and
             {
                 if (ra == b1111)
                     result = armv7_read_thumb_32_instr_mul(raw);
+
                 else
                     result = armv7_read_thumb_32_instr_mla(raw);
+
             }
 
             else if (op2 == b01)
@@ -1629,6 +2013,7 @@ static GArchInstruction *process_armv7_thumb_32_multiply_multiply_accumulate_and
 
             if (ra == b1111)
                 result = armv7_read_thumb_32_instr_smulbb_smulbt_smultb_smultt(raw);
+
             else
                 result = armv7_read_thumb_32_instr_smlabb_smlabt_smlatb_smlatt(raw);
 
@@ -1639,8 +2024,10 @@ static GArchInstruction *process_armv7_thumb_32_multiply_multiply_accumulate_and
             {
                 if (ra == b1111)
                     result = armv7_read_thumb_32_instr_smuad(raw);
+
                 else
                     result = armv7_read_thumb_32_instr_smlad(raw);
+
             }
             break;
 
@@ -1649,8 +2036,10 @@ static GArchInstruction *process_armv7_thumb_32_multiply_multiply_accumulate_and
             {
                 if (ra == b1111)
                     result = armv7_read_thumb_32_instr_smulwb_smulwt(raw);
+
                 else
                     result = armv7_read_thumb_32_instr_smlawb_smlawt(raw);
+
             }
             break;
 
@@ -1659,8 +2048,10 @@ static GArchInstruction *process_armv7_thumb_32_multiply_multiply_accumulate_and
             {
                 if (ra == b1111)
                     result = armv7_read_thumb_32_instr_smusd(raw);
+
                 else
                     result = armv7_read_thumb_32_instr_smlsd(raw);
+
             }
             break;
 
@@ -1669,8 +2060,10 @@ static GArchInstruction *process_armv7_thumb_32_multiply_multiply_accumulate_and
             {
                 if (ra == b1111)
                     result = armv7_read_thumb_32_instr_smmul(raw);
+
                 else
                     result = armv7_read_thumb_32_instr_smmla(raw);
+
             }
             break;
 
@@ -1684,8 +2077,10 @@ static GArchInstruction *process_armv7_thumb_32_multiply_multiply_accumulate_and
             {
                 if (ra == b1111)
                     result = armv7_read_thumb_32_instr_usad8(raw);
+
                 else
                     result = armv7_read_thumb_32_instr_usada8(raw);
+
             }
             break;
 
@@ -1700,7 +2095,7 @@ static GArchInstruction *process_armv7_thumb_32_multiply_multiply_accumulate_and
 *                                                                             *
 *  Paramètres  : raw = donnée brute de 32 bits à désassembler.                *
 *                                                                             *
-*  Description : Désassemble une instruction ARMv7 classique.                 *
+*  Description : Désassemble une instruction ARMv7 liées au chapitre A6.3.17. *
 *                                                                             *
 *  Retour      : Instruction mise en place ou NULL en cas d'échec.            *
 *                                                                             *
@@ -1783,18 +2178,104 @@ static GArchInstruction *process_armv7_thumb_32_long_multiply_long_multiply_accu
 }
 
 
+/******************************************************************************
+*                                                                             *
+*  Paramètres  : raw = donnée brute de 32 bits à désassembler.                *
+*                                                                             *
+*  Description : Désassemble une instruction ARMv7 liées au chapitre A6.3.18. *
+*                                                                             *
+*  Retour      : Instruction mise en place ou NULL en cas d'échec.            *
+*                                                                             *
+*  Remarques   : -                                                            *
+*                                                                             *
+******************************************************************************/
+
+static GArchInstruction *process_armv7_thumb_32_coprocessor_advanced_simd_and_floating_point_instructions(uint32_t raw)
+{
+    GArchInstruction *result;               /* Instruction à renvoyer      */
+    uint32_t op1;                           /* Champ 'op1' à retrouver     */
+    uint32_t rn;                            /* Champ 'rn' à retrouver      */
+    uint32_t coproc;                        /* Champ 'coproc' à retrouver  */
+    uint32_t op;                            /* Champ 'op' à retrouver      */
+
+    /**
+     * Suit les directives de :
+     * § A6.3.18 Coprocessor, Advanced SIMD, and Floating-point instructions
+     */
+
+    if ((raw & 0xec000000) != 0xec000000) return NULL;
+
+    result = NULL;
+
+    op1 = (raw >> 20) & 0x3f;
+    rn = (raw >> 16) & 0xf;
+    coproc = (raw >> 8) & 0xf;
+    op = (raw >> 4) & 0x1;
+
+    if ((op1 & b111110) == b000000)
+        /* UNDEFINED */
+        assert(false);
+
+    else if ((op1 & b110000) == b110000)
+        /* Advanced SIMD data-processing instructions on page A7-261 */
+        assert(false);
 
+    else if ((coproc & b1110) != b1010)
+    {
+        if ((op1 & b100001) == b000000 && (op1 & b111010) != b000000)
+            result = armv7_read_thumb_32_instr_stc_stc2(raw);
+
+        else if ((op1 & b100001) == b000001 && (op1 & b111010) != b000000)
+        {
+            if (rn != b1111)
+                result = armv7_read_thumb_32_instr_ldc_ldc2_immediate(raw);
+
+            else/* if (rn == b1111)*/
+                result = armv7_read_thumb_32_instr_ldc_ldc2_literal(raw);
+
+        }
 
+        else if (op1 == b000100)
+            result = armv7_read_thumb_32_instr_mcrr_mcrr2(raw);
 
+        else if (op1 == b000101)
+            result = armv7_read_thumb_32_instr_mrrc_mrrc2(raw);
 
+        else if ((op1 & b110000) == b100000 && op == b0)
+            result = armv7_read_thumb_32_instr_cdp_cdp2(raw);
 
+        else if ((op1 & b110001) == b100000 && op == b1)
+            result = armv7_read_thumb_32_instr_mcr_mcr2(raw);
 
+        else if ((op1 & b110001) == b100001 && op == b1)
+            result = armv7_read_thumb_32_instr_mrc_mrc2(raw);
 
+    }
 
+    else if ((coproc & b1110) == b1010)
+    {
+        if ((op1 & b100000) == b000000 && (op1 & b111010) != b000000)
+            /* Extension register load/store instructions on page A7-274 */
+            assert(false);
 
+        else if ((op1 & b111110) == b000100)
+            /* 64-bit transfers between ARM core and extension registers on page A7-279 */
+            assert(false);
 
+        else if ((op1 & b110000) == b100000)
+        {
+            if (op == b0)
+                /* Floating-point data-processing instructions on page A7-272 */
+                assert(false);
 
+            else/* if (op == b1)*/
+                /* 8, 16, and 32-bit transfer between ARM core and extension registers on page A7-278 */
+                assert(false);
 
+        }
 
+    }
 
+    return result;
 
+}
diff --git a/src/arch/arm/v7/thumb_32.h b/src/arch/arm/v7/thumb_32.h
index 57061f8..83e5ecb 100644
--- a/src/arch/arm/v7/thumb_32.h
+++ b/src/arch/arm/v7/thumb_32.h
@@ -29,7 +29,7 @@
 
 
 
-/* Désassemble une instruction ARMv7 en mode Thumb 32 bits. */
+/* Désassemble une instruction ARMv7 liées au chapitre A6.3. */
 GArchInstruction *process_armv7_thumb_32_instruction_set_encoding(uint32_t);