Prepared the ARMv7 SIMD instructions support.

7 files changed, 1752 insertions, 28 deletions

diff --git a/src/arch/arm/v7/Makefile.am b/src/arch/arm/v7/Makefile.am
index f9b35b6..cea4dda 100644
--- a/src/arch/arm/v7/Makefile.am
+++ b/src/arch/arm/v7/Makefile.am
@@ -11,6 +11,7 @@ libarcharmv7_la_SOURCES =				\
 	processor.h processor.c				\
 	pseudo.h pseudo.c					\
 	register.h register.c				\
+	simd.h simd.c						\
 	thumb_16.h thumb_16.c				\
 	thumb_32.h thumb_32.c
 
diff --git a/src/arch/arm/v7/arm.c b/src/arch/arm/v7/arm.c
index 542d521..af92096 100644
--- a/src/arch/arm/v7/arm.c
+++ b/src/arch/arm/v7/arm.c
@@ -24,10 +24,10 @@
 #include "arm.h"
 
 
-#include <assert.h>
 #include <stdint.h>
 
 
+#include "simd.h"
 #include "opcodes/arm_opcodes.h"
 #include "opcodes/opcodes_tmp_arm.h"
 #include "../../undefined.h"
@@ -2241,12 +2241,10 @@ static GArchInstruction *process_armv7_arm_memory_hints_advanced_simd_instructio
     }
 
     else if ((op1 & b1100000) == b0100000)
-        /* Advanced SIMD data-processing instructions */
-        assert(false);
+        result = process_armv7_simd_advanced_simd_data_processing_instructions(raw, true);
 
     else if ((op1 & b1110001) == b1000000)
-        /* Advanced SIMD element or structure load/store instructions */
-        assert(false);
+        result = process_armv7_simd_advanced_simd_element_or_structure_load_store_instructions(raw, true);
 
     else if ((op1 & b1110111) == b1000001)
         result = g_undef_instruction_new(IBS_NOP);
diff --git a/src/arch/arm/v7/build_tmp_decl.sh b/src/arch/arm/v7/build_tmp_decl.sh
index 0b4c2bc..0d0feee 100755
--- a/src/arch/arm/v7/build_tmp_decl.sh
+++ b/src/arch/arm/v7/build_tmp_decl.sh
@@ -19,7 +19,11 @@ for n in $needed; do
 	test -f $header && grep -q "$n(" $header
 	if [ $? -ne 0 ]; then
 
-		echo "#define $n(r) NULL" >> $headertmp
+		if [ $arch = "simd" ]; then
+			echo "#define $n(r, a) NULL" >> $headertmp
+		else
+			echo "#define $n(r) NULL" >> $headertmp
+		fi
 
 	else
 
diff --git a/src/arch/arm/v7/opcodes/opcodes_tmp_simd.h b/src/arch/arm/v7/opcodes/opcodes_tmp_simd.h
new file mode 100644
index 0000000..1d7023e
--- /dev/null
+++ b/src/arch/arm/v7/opcodes/opcodes_tmp_simd.h
@@ -0,0 +1,138 @@
+#ifndef simd_def_tmp_h
+#define simd_def_tmp_h
+#define armv7_read_simd_instr_vaba_vabal(r, a) NULL
+#define armv7_read_simd_instr_vabd_floating_point(r, a) NULL
+#define armv7_read_simd_instr_vabd_vabdl_integer(r, a) NULL
+#define armv7_read_simd_instr_vabs(r, a) NULL
+#define armv7_read_simd_instr_vacge_vacgt_vacle_vaclt(r, a) NULL
+#define armv7_read_simd_instr_vadd_floating_point(r, a) NULL
+#define armv7_read_simd_instr_vaddhn(r, a) NULL
+#define armv7_read_simd_instr_vadd_integer(r, a) NULL
+#define armv7_read_simd_instr_vaddl_vaddw(r, a) NULL
+#define armv7_read_simd_instr_vand_register(r, a) NULL
+#define armv7_read_simd_instr_vbic_immediate(r, a) NULL
+#define armv7_read_simd_instr_vbic_register(r, a) NULL
+#define armv7_read_simd_instr_vbif_vbit_vbsl(r, a) NULL
+#define armv7_read_simd_instr_vceq_immediate_0(r, a) NULL
+#define armv7_read_simd_instr_vceq_register(r, a) NULL
+#define armv7_read_simd_instr_vcge_immediate_0(r, a) NULL
+#define armv7_read_simd_instr_vcge_register(r, a) NULL
+#define armv7_read_simd_instr_vcgt_immediate_0(r, a) NULL
+#define armv7_read_simd_instr_vcgt_register(r, a) NULL
+#define armv7_read_simd_instr_vcle_immediate_0(r, a) NULL
+#define armv7_read_simd_instr_vcls(r, a) NULL
+#define armv7_read_simd_instr_vclt_immediate_0(r, a) NULL
+#define armv7_read_simd_instr_vclz(r, a) NULL
+#define armv7_read_simd_instr_vcmp_vcmpe(r, a) NULL
+#define armv7_read_simd_instr_vcnt(r, a) NULL
+#define armv7_read_simd_instr_vcvt_between_double_precision_and_single_precision(r, a) NULL
+#define armv7_read_simd_instr_vcvt_between_floating_point_and_fixed_point_advanced_simd(r, a) NULL
+#define armv7_read_simd_instr_vcvt_between_floating_point_and_fixed_point_floating_point(r, a) NULL
+#define armv7_read_simd_instr_vcvtb_vcvtt(r, a) NULL
+#define armv7_read_simd_instr_vcvt_vcvtr_between_floating_point_and_integer_floating_point(r, a) NULL
+#define armv7_read_simd_instr_vdiv(r, a) NULL
+#define armv7_read_simd_instr_vdup_arm_core_register(r, a) NULL
+#define armv7_read_simd_instr_vdup_scalar(r, a) NULL
+#define armv7_read_simd_instr_veor(r, a) NULL
+#define armv7_read_simd_instr_vext(r, a) NULL
+#define armv7_read_simd_instr_vfma_vfms(r, a) NULL
+#define armv7_read_simd_instr_vfnma_vfnms(r, a) NULL
+#define armv7_read_simd_instr_vhadd_vhsub(r, a) NULL
+#define armv7_read_simd_instr_vld1_multiple_single_elements(r, a) NULL
+#define armv7_read_simd_instr_vld1_single_element_to_all_lanes(r, a) NULL
+#define armv7_read_simd_instr_vld1_single_element_to_one_lane(r, a) NULL
+#define armv7_read_simd_instr_vld2_multiple_2_element_structures(r, a) NULL
+#define armv7_read_simd_instr_vld2_single_2_element_structure_to_all_lanes(r, a) NULL
+#define armv7_read_simd_instr_vld2_single_2_element_structure_to_one_lane(r, a) NULL
+#define armv7_read_simd_instr_vld3_multiple_3_element_structures(r, a) NULL
+#define armv7_read_simd_instr_vld3_single_3_element_structure_to_all_lanes(r, a) NULL
+#define armv7_read_simd_instr_vld3_single_3_element_structure_to_one_lane(r, a) NULL
+#define armv7_read_simd_instr_vld4_multiple_4_element_structures(r, a) NULL
+#define armv7_read_simd_instr_vld4_single_4_element_structure_to_all_lanes(r, a) NULL
+#define armv7_read_simd_instr_vld4_single_4_element_structure_to_one_lane(r, a) NULL
+#define armv7_read_simd_instr_vldm(r, a) NULL
+#define armv7_read_simd_instr_vldr(r, a) NULL
+#define armv7_read_simd_instr_vmax_vmin_floating_point(r, a) NULL
+#define armv7_read_simd_instr_vmax_vmin_integer(r, a) NULL
+#define armv7_read_simd_instr_vmla_vmlal_vmls_vmlsl_by_scalar(r, a) NULL
+#define armv7_read_simd_instr_vmla_vmlal_vmls_vmlsl_integer(r, a) NULL
+#define armv7_read_simd_instr_vmla_vmls_floating_point(r, a) NULL
+#define armv7_read_simd_instr_vmov_arm_core_register_to_scalar(r, a) NULL
+#define armv7_read_simd_instr_vmov_between_arm_core_register_and_single_precision_register(r, a) NULL
+#define armv7_read_simd_instr_vmov_between_two_arm_core_registers_and_a_doubleword_extension_register(r, a) NULL
+#define armv7_read_simd_instr_vmov_between_two_arm_core_registers_and_two_single_precision_registers(r, a) NULL
+#define armv7_read_simd_instr_vmov_immediate(r, a) NULL
+#define armv7_read_simd_instr_vmovl(r, a) NULL
+#define armv7_read_simd_instr_vmov_register(r, a) NULL
+#define armv7_read_simd_instr_vmov_scalar_to_arm_core_register(r, a) NULL
+#define armv7_read_simd_instr_vmrs(r, a) NULL
+#define armv7_read_simd_instr_vmrs_b9(r, a) NULL
+#define armv7_read_simd_instr_vmsr(r, a) NULL
+#define armv7_read_simd_instr_vmsr_b9(r, a) NULL
+#define armv7_read_simd_instr_vmul_floating_point(r, a) NULL
+#define armv7_read_simd_instr_vmul_vmull_by_scalar(r, a) NULL
+#define armv7_read_simd_instr_vmul_vmull_integer_and_polynomial(r, a) NULL
+#define armv7_read_simd_instr_vmvn_immediate(r, a) NULL
+#define armv7_read_simd_instr_vmvn_register(r, a) NULL
+#define armv7_read_simd_instr_vneg(r, a) NULL
+#define armv7_read_simd_instr_vnmla_vnmls_vnmul(r, a) NULL
+#define armv7_read_simd_instr_vorn_register(r, a) NULL
+#define armv7_read_simd_instr_vorr_immediate(r, a) NULL
+#define armv7_read_simd_instr_vorr_register(r, a) NULL
+#define armv7_read_simd_instr_vpadal(r, a) NULL
+#define armv7_read_simd_instr_vpadd_floating_point(r, a) NULL
+#define armv7_read_simd_instr_vpadd_integer(r, a) NULL
+#define armv7_read_simd_instr_vpaddl(r, a) NULL
+#define armv7_read_simd_instr_vpmax_vpmin_floating_point(r, a) NULL
+#define armv7_read_simd_instr_vpmax_vpmin_integer(r, a) NULL
+#define armv7_read_simd_instr_vpop(r, a) NULL
+#define armv7_read_simd_instr_vpush(r, a) NULL
+#define armv7_read_simd_instr_vqabs(r, a) NULL
+#define armv7_read_simd_instr_vqadd(r, a) NULL
+#define armv7_read_simd_instr_vqdmlal_vqdmlsl(r, a) NULL
+#define armv7_read_simd_instr_vqdmulh(r, a) NULL
+#define armv7_read_simd_instr_vqdmull(r, a) NULL
+#define armv7_read_simd_instr_vqneg(r, a) NULL
+#define armv7_read_simd_instr_vqrdmulh(r, a) NULL
+#define armv7_read_simd_instr_vqrshl(r, a) NULL
+#define armv7_read_simd_instr_vqrshrn_vqrshrun(r, a) NULL
+#define armv7_read_simd_instr_vqshl_register(r, a) NULL
+#define armv7_read_simd_instr_vqshl_vqshlu_immediate(r, a) NULL
+#define armv7_read_simd_instr_vqshrn_vqshrun(r, a) NULL
+#define armv7_read_simd_instr_vqsub(r, a) NULL
+#define armv7_read_simd_instr_vraddhn(r, a) NULL
+#define armv7_read_simd_instr_vrecps(r, a) NULL
+#define armv7_read_simd_instr_vrev16_vrev32_vrev64(r, a) NULL
+#define armv7_read_simd_instr_vrhadd(r, a) NULL
+#define armv7_read_simd_instr_vrshl(r, a) NULL
+#define armv7_read_simd_instr_vrshr(r, a) NULL
+#define armv7_read_simd_instr_vrshrn(r, a) NULL
+#define armv7_read_simd_instr_vrsqrts(r, a) NULL
+#define armv7_read_simd_instr_vrsra(r, a) NULL
+#define armv7_read_simd_instr_vrsubhn(r, a) NULL
+#define armv7_read_simd_instr_vshl_immediate(r, a) NULL
+#define armv7_read_simd_instr_vshll(r, a) NULL
+#define armv7_read_simd_instr_vshl_register(r, a) NULL
+#define armv7_read_simd_instr_vshr(r, a) NULL
+#define armv7_read_simd_instr_vshrn(r, a) NULL
+#define armv7_read_simd_instr_vsli(r, a) NULL
+#define armv7_read_simd_instr_vsqrt(r, a) NULL
+#define armv7_read_simd_instr_vsra(r, a) NULL
+#define armv7_read_simd_instr_vsri(r, a) NULL
+#define armv7_read_simd_instr_vst1_multiple_single_elements(r, a) NULL
+#define armv7_read_simd_instr_vst1_single_element_from_one_lane(r, a) NULL
+#define armv7_read_simd_instr_vst2_multiple_2_element_structures(r, a) NULL
+#define armv7_read_simd_instr_vst2_single_2_element_structure_from_one_lane(r, a) NULL
+#define armv7_read_simd_instr_vst3_multiple_3_element_structures(r, a) NULL
+#define armv7_read_simd_instr_vst3_single_3_element_structure_from_one_lane(r, a) NULL
+#define armv7_read_simd_instr_vst4_multiple_4_element_structures(r, a) NULL
+#define armv7_read_simd_instr_vst4_single_4_element_structure_from_one_lane(r, a) NULL
+#define armv7_read_simd_instr_vstm(r, a) NULL
+#define armv7_read_simd_instr_vstr(r, a) NULL
+#define armv7_read_simd_instr_vsub_floating_point(r, a) NULL
+#define armv7_read_simd_instr_vsubhn(r, a) NULL
+#define armv7_read_simd_instr_vsub_integer(r, a) NULL
+#define armv7_read_simd_instr_vsubl_vsubw(r, a) NULL
+#define armv7_read_simd_instr_vtbl_vtbx(r, a) NULL
+#define armv7_read_simd_instr_vtst(r, a) NULL
+#endif
diff --git a/src/arch/arm/v7/simd.c b/src/arch/arm/v7/simd.c
new file mode 100644
index 0000000..48ba0dc
--- /dev/null
+++ b/src/arch/arm/v7/simd.c
@@ -0,0 +1,1539 @@
+
+/* Chrysalide - Outil d'analyse de fichiers binaires
+ * simd.c - désassemblage des instructions ARMv7 SIMD
+ *
+ * Copyright (C) 2016 Cyrille Bagard
+ *
+ *  This file is part of Chrysalide.
+ *
+ *  OpenIDA is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 3 of the License, or
+ *  (at your option) any later version.
+ *
+ *  OpenIDA is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Foobar.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+#include "simd.h"
+
+
+#include <stdint.h>
+
+
+//#include "opcodes/simd_opcodes.h"
+#include "opcodes/opcodes_tmp_simd.h"
+#include "../../undefined.h"
+#include "../../../common/bconst.h"
+
+
+
+/* Désassemble une instruction ARMv7 liées au chapitre A7.4.1. */
+static GArchInstruction *process_armv7_simd_three_registers_of_the_same_length(uint32_t, bool);
+
+/* Désassemble une instruction ARMv7 liées au chapitre A7.4.2. */
+static GArchInstruction *process_armv7_simd_three_registers_of_different_lengths(uint32_t, bool);
+
+/* Désassemble une instruction ARMv7 liées au chapitre A7.4.3. */
+static GArchInstruction *process_armv7_simd_two_registers_and_a_scalar(uint32_t, bool);
+
+/* Désassemble une instruction ARMv7 liées au chapitre A7.4.4. */
+static GArchInstruction *process_armv7_simd_two_registers_and_a_shift_amount(uint32_t, bool);
+
+/* Désassemble une instruction ARMv7 liées au chapitre A7.4.5. */
+static GArchInstruction *process_armv7_simd_two_registers_miscellaneous(uint32_t, bool);
+
+/* Désassemble une instruction ARMv7 liées au chapitre A7.4.6. */
+static GArchInstruction *process_armv7_simd_one_register_and_a_modified_immediate_value(uint32_t, bool);
+
+
+
+/******************************************************************************
+*                                                                             *
+*  Paramètres  : raw = donnée brute de 16 bits à désassembler.                *
+*                arm = précise si l'encodage est en mode ARM ou Thumb.        *
+*                                                                             *
+*  Description : Désassemble une instruction ARMv7 liées au chapitre A7.4.    *
+*                                                                             *
+*  Retour      : Instruction mise en place ou NULL en cas d'échec.            *
+*                                                                             *
+*  Remarques   : -                                                            *
+*                                                                             *
+******************************************************************************/
+
+GArchInstruction *process_armv7_simd_advanced_simd_data_processing_instructions(uint32_t raw, bool arm)
+{
+    GArchInstruction *result;               /* Instruction à renvoyer      */
+    uint32_t u;                             /* Champ 'u' à retrouver       */
+    uint32_t a;                             /* Champ 'a' à retrouver       */
+    uint32_t b;                             /* Champ 'b' à retrouver       */
+    uint32_t c;                             /* Champ 'c' à retrouver       */
+
+    /**
+     * Suit les directives de :
+     * § A7.4 Advanced SIMD data-processing instructions
+     */
+
+    if (arm)
+    {
+        if ((raw & 0xfe000000) != 0xf2000000) return NULL;
+    }
+    else
+    {
+        if ((raw & 0xef000000) != 0xef000000) return NULL;
+    }
+
+    result = NULL;
+
+    if (arm)
+    {
+        u = (raw >> 24) & b1;
+        a = (raw >> 19) & b11111;
+        b = (raw >> 8) & b1111;
+        c = (raw >> 4) & b1111;
+    }
+    else
+    {
+        u = (raw >> 28) & b1;
+        a = (raw >> 19) & b11111;
+        b = (raw >> 8) & b1111;
+        c = (raw >> 4) & b1111;
+    }
+
+    if ((a & b10000) == b00000)
+        result = process_armv7_simd_three_registers_of_the_same_length(raw, arm);
+
+    else if ((a & b10111) == b10000 && (c & b1001) == b0001)
+        result = process_armv7_simd_one_register_and_a_modified_immediate_value(raw, arm);
+
+    else if ((a & b10111) == b10001 && (c & b1001) == b0001)
+        result = process_armv7_simd_two_registers_and_a_shift_amount(raw, arm);
+
+    else if ((a & b10110) == b10010 && (c & b1001) == b0001)
+        result = process_armv7_simd_two_registers_and_a_shift_amount(raw, arm);
+
+    else if ((a & b10100) == b10100 && (c & b1001) == b0001)
+        result = process_armv7_simd_two_registers_and_a_shift_amount(raw, arm);
+
+    else if ((a & b10000) == b10000 && (c & b1001) == b1001)
+        result = process_armv7_simd_two_registers_and_a_shift_amount(raw, arm);
+
+    else if ((a & b10100) == b10000 && (c & b0101) == b0000)
+        result = process_armv7_simd_three_registers_of_different_lengths(raw, arm);
+
+    else if ((a & b10110) == b10100 && (c & b0101) == b0000)
+        result = process_armv7_simd_three_registers_of_different_lengths(raw, arm);
+
+    else if ((a & b10100) == b10000 && (c & b0101) == b0100)
+        result = process_armv7_simd_two_registers_and_a_scalar(raw, arm);
+
+    else if ((a & b10110) == b10100 && (c & b0101) == b0100)
+        result = process_armv7_simd_two_registers_and_a_scalar(raw, arm);
+
+    else if (u == b0 && (a & b10110) == b10110 && (c & b0001) == b0000)
+        result = armv7_read_simd_instr_vext(raw, arm);
+
+    else if (u == b1 && (a & b10110) == b10110)
+    {
+        if ((b & b1000) == b0000 && (c & b0001) == b0000)
+            result = process_armv7_simd_two_registers_miscellaneous(raw, arm);
+
+        else if ((b & b1100) == b1000 && (c & b0001) == b0000)
+            result = armv7_read_simd_instr_vtbl_vtbx(raw, arm);
+
+        else if (b == b1100 && (c & b1001) == b0000)
+            result = armv7_read_simd_instr_vdup_scalar(raw, arm);
+
+    }
+
+    return result;
+
+}
+
+
+/******************************************************************************
+*                                                                             *
+*  Paramètres  : raw = donnée brute de 16 bits à désassembler.                *
+*                arm = précise si l'encodage est en mode ARM ou Thumb.        *
+*                                                                             *
+*  Description : Désassemble une instruction ARMv7 liées au chapitre A7.4.1.  *
+*                                                                             *
+*  Retour      : Instruction mise en place ou NULL en cas d'échec.            *
+*                                                                             *
+*  Remarques   : -                                                            *
+*                                                                             *
+******************************************************************************/
+
+static GArchInstruction *process_armv7_simd_three_registers_of_the_same_length(uint32_t raw, bool arm)
+{
+    GArchInstruction *result;               /* Instruction à renvoyer      */
+    uint32_t u;                             /* Champ 'u' à retrouver       */
+    uint32_t c;                             /* Champ 'c' à retrouver       */
+    uint32_t a;                             /* Champ 'a' à retrouver       */
+    uint32_t b;                             /* Champ 'b' à retrouver       */
+
+    /**
+     * Suit les directives de :
+     * § A7.4.1 Three registers of the same length
+     */
+
+    if (arm)
+    {
+        if ((raw & 0xfe800000) != 0xf2000000) return NULL;
+    }
+    else
+    {
+        if ((raw & 0xef800000) != 0xef000000) return NULL;
+    }
+
+    result = NULL;
+
+    if (arm)
+    {
+        u = (raw >> 24) & b1;
+        c = (raw >> 20) & b11;
+        a = (raw >> 8) & b1111;
+        b = (raw >> 4) & b1;
+    }
+    else
+    {
+        u = (raw >> 28) & b1;
+        c = (raw >> 20) & b11;
+        a = (raw >> 8) & b1111;
+        b = (raw >> 4) & b1;
+    }
+
+    if (a == b0000)
+    {
+        if (b == b0)
+            result = armv7_read_simd_instr_vhadd_vhsub(raw, arm);
+
+        else/* if (b == b1)*/
+            result = armv7_read_simd_instr_vqadd(raw, arm);
+
+    }
+
+    else if (a == b0001)
+    {
+        if (b == b0)
+            result = armv7_read_simd_instr_vrhadd(raw, arm);
+
+        else/* if (b == b1)*/
+        {
+            if (u == b0)
+                switch (c)
+                {
+                    case b00:
+                        result = armv7_read_simd_instr_vand_register(raw, arm);
+                        break;
+
+                    case b01:
+                        result = armv7_read_simd_instr_vbic_register(raw, arm);
+                        break;
+
+                    case b10:
+                        /* Cf. vmov_register aussi */
+                        result = armv7_read_simd_instr_vorr_register(raw, arm);
+                        break;
+
+                     case b11:
+                        result = armv7_read_simd_instr_vorn_register(raw, arm);
+                        break;
+
+                }
+
+            else/* if (u == b1)*/
+                switch (c)
+                {
+                    case b00:
+                        result = armv7_read_simd_instr_veor(raw, arm);
+                        break;
+
+                    case b01:
+                        result = armv7_read_simd_instr_vbif_vbit_vbsl(raw, arm);
+                        break;
+
+                    case b10:
+                        result = armv7_read_simd_instr_vbif_vbit_vbsl(raw, arm);
+                        break;
+
+                     case b11:
+                        result = armv7_read_simd_instr_vbif_vbit_vbsl(raw, arm);
+                        break;
+
+                }
+
+        }
+
+    }
+
+    else if (a == b0010)
+    {
+        if (b == b0)
+            result = armv7_read_simd_instr_vhadd_vhsub(raw, arm);
+
+        else/* if (b == b1)*/
+            result = armv7_read_simd_instr_vqsub(raw, arm);
+
+    }
+
+    else if (a == b0011)
+    {
+        if (b == b0)
+            result = armv7_read_simd_instr_vcgt_register(raw, arm);
+
+        else/* if (b == b1)*/
+            result = armv7_read_simd_instr_vcge_register(raw, arm);
+
+    }
+
+    else if (a == b0100)
+    {
+        if (b == b0)
+            result = armv7_read_simd_instr_vshl_register(raw, arm);
+
+        else/* if (b == b1)*/
+            result = armv7_read_simd_instr_vqshl_register(raw, arm);
+
+    }
+
+    else if (a == b0101)
+    {
+        if (b == b0)
+            result = armv7_read_simd_instr_vrshl(raw, arm);
+
+        else/* if (b == b1)*/
+            result = armv7_read_simd_instr_vqrshl(raw, arm);
+
+    }
+
+    else if (a == b0110)
+        result = armv7_read_simd_instr_vmax_vmin_integer(raw, arm);
+
+    else if (a == b0111)
+    {
+        if (b == b0)
+            result = armv7_read_simd_instr_vabd_vabdl_integer(raw, arm);
+
+        else/* if (b == b1)*/
+            result = armv7_read_simd_instr_vaba_vabal(raw, arm);
+
+    }
+
+    else if (a == b1000)
+    {
+        if (b == b0)
+        {
+            if (u == b0)
+                result = armv7_read_simd_instr_vadd_integer(raw, arm);
+
+            else/* if (u == b1)*/
+                result = armv7_read_simd_instr_vsub_integer(raw, arm);
+
+        }
+
+        else/* if (b == b1)*/
+        {
+            if (u == b0)
+                result = armv7_read_simd_instr_vtst(raw, arm);
+
+            else/* if (u == b1)*/
+                result = armv7_read_simd_instr_vceq_register(raw, arm);
+
+        }
+
+    }
+
+    else if (a == b1001)
+    {
+        if (b == b0)
+            result = armv7_read_simd_instr_vmla_vmlal_vmls_vmlsl_integer(raw, arm);
+
+        else/* if (b == b1)*/
+            result = armv7_read_simd_instr_vmul_vmull_integer_and_polynomial(raw, arm);
+
+    }
+
+    else if (a == b1010)
+        result = armv7_read_simd_instr_vpmax_vpmin_integer(raw, arm);
+
+    else if (a == b1011)
+    {
+        if (b == b0)
+        {
+            if (u == b0)
+                result = armv7_read_simd_instr_vqdmulh(raw, arm);
+
+            else/* if (u == b1)*/
+                result = armv7_read_simd_instr_vqrdmulh(raw, arm);
+
+        }
+
+        else/* if (b == b1)*/
+        {
+            if (u == b0)
+                result = armv7_read_simd_instr_vpadd_integer(raw, arm);
+
+        }
+
+    }
+
+    else if (a == b1100)
+    {
+        if (b == b1 && u == b0)
+            result = armv7_read_simd_instr_vfma_vfms(raw, arm);
+
+    }
+
+    else if (a == b1101)
+    {
+        if (b == b0)
+        {
+            if (u == b0)
+            {
+                if ((c & b10) == b00)
+                    result = armv7_read_simd_instr_vadd_floating_point(raw, arm);
+
+                else/* if ((c & b10) == b10)*/
+                    result = armv7_read_simd_instr_vsub_floating_point(raw, arm);
+
+            }
+
+            else/* if (u == b1)*/
+            {
+                if ((c & b10) == b00)
+                    result = armv7_read_simd_instr_vpadd_floating_point(raw, arm);
+
+                else/* if ((c & b10) == b10)*/
+                    result = armv7_read_simd_instr_vabd_floating_point(raw, arm);
+
+            }
+
+        }
+
+        else/* if (b == b1)*/
+        {
+            if (u == b0)
+                result = armv7_read_simd_instr_vmla_vmls_floating_point(raw, arm);
+
+            else/* if (u == b1)*/
+            {
+                if ((c & b10) == b00)
+                    result = armv7_read_simd_instr_vmul_floating_point(raw, arm);
+
+            }
+
+        }
+
+    }
+
+    else if (a == b1110)
+    {
+        if (b == b0)
+        {
+            if (u == b0)
+            {
+                if ((c & b10) == b00)
+                    result = armv7_read_simd_instr_vceq_register(raw, arm);
+
+            }
+
+            else/* if (u == b1)*/
+            {
+                if ((c & b10) == b00)
+                    result = armv7_read_simd_instr_vcge_register(raw, arm);
+
+                else/* if ((c & b10) == b10)*/
+                    result = armv7_read_simd_instr_vcgt_register(raw, arm);
+
+            }
+
+        }
+
+        else/* if (b == b1)*/
+        {
+            if (u == b1)
+                result = armv7_read_simd_instr_vacge_vacgt_vacle_vaclt(raw, arm);
+
+        }
+
+    }
+
+    else if (a == b1111)
+    {
+        if (b == b0)
+        {
+            if (u == b0)
+                result = armv7_read_simd_instr_vmax_vmin_floating_point(raw, arm);
+
+            else/* if (u == b1)*/
+                result = armv7_read_simd_instr_vpmax_vpmin_floating_point(raw, arm);
+
+        }
+
+        else/* if (b == b1)*/
+        {
+            if (u == b0)
+            {
+                if ((c & b10) == b00)
+                    result = armv7_read_simd_instr_vrecps(raw, arm);
+
+                else/* if ((c & b10) == b10)*/
+                    result = armv7_read_simd_instr_vrsqrts(raw, arm);
+
+            }
+
+        }
+
+    }
+
+    return result;
+
+}
+
+
+/******************************************************************************
+*                                                                             *
+*  Paramètres  : raw = donnée brute de 16 bits à désassembler.                *
+*                arm = précise si l'encodage est en mode ARM ou Thumb.        *
+*                                                                             *
+*  Description : Désassemble une instruction ARMv7 liées au chapitre A7.4.2.  *
+*                                                                             *
+*  Retour      : Instruction mise en place ou NULL en cas d'échec.            *
+*                                                                             *
+*  Remarques   : -                                                            *
+*                                                                             *
+******************************************************************************/
+
+static GArchInstruction *process_armv7_simd_three_registers_of_different_lengths(uint32_t raw, bool arm)
+{
+    GArchInstruction *result;               /* Instruction à renvoyer      */
+    uint32_t u;                             /* Champ 'u' à retrouver       */
+    uint32_t a;                             /* Champ 'a' à retrouver       */
+
+    /**
+     * Suit les directives de :
+     * § A7.4.2 Three registers of different lengths
+     */
+
+    if (arm)
+    {
+        if ((raw & 0xfe800050) != 0xf2800000) return NULL;
+    }
+    else
+    {
+        if ((raw & 0xef800050) != 0xef800000) return NULL;
+    }
+
+    result = NULL;
+
+    if (arm)
+    {
+        u = (raw >> 24) & b1;
+        a = (raw >> 8) & b1111;
+    }
+    else
+    {
+        u = (raw >> 28) & b1;
+        a = (raw >> 8) & b1111;
+    }
+
+    if ((a & b1110) == b0000)
+        result = armv7_read_simd_instr_vaddl_vaddw(raw, arm);
+
+    else if ((a & b1110) == b0010)
+        result = armv7_read_simd_instr_vsubl_vsubw(raw, arm);
+
+    else if (a == b0100)
+    {
+        if (u == b0)
+            result = armv7_read_simd_instr_vaddhn(raw, arm);
+
+        else/* if (u == b1)*/
+            result = armv7_read_simd_instr_vraddhn(raw, arm);
+
+    }
+
+    else if (a == b0101)
+        result = armv7_read_simd_instr_vaba_vabal(raw, arm);
+
+    else if (a == b0110)
+    {
+        if (u == b0)
+            result = armv7_read_simd_instr_vsubhn(raw, arm);
+
+        else/* if (u == b1)*/
+            result = armv7_read_simd_instr_vrsubhn(raw, arm);
+
+    }
+
+    else if (a == b0111)
+        result = armv7_read_simd_instr_vabd_vabdl_integer(raw, arm);
+
+    else if ((a & b1101) == b1000)
+        result = armv7_read_simd_instr_vmla_vmlal_vmls_vmlsl_integer(raw, arm);
+
+    else if ((a & b1101) == b1001)
+    {
+        if (u == b0)
+            result = armv7_read_simd_instr_vqdmlal_vqdmlsl(raw, arm);
+
+    }
+
+    else if (a == b1100)
+        result = armv7_read_simd_instr_vmul_vmull_integer_and_polynomial(raw, arm);
+
+    else if (a == b1101)
+    {
+        if (u == b0)
+            result = armv7_read_simd_instr_vqdmull(raw, arm);
+
+    }
+
+    else if (a == b1110)
+        result = armv7_read_simd_instr_vmul_vmull_integer_and_polynomial(raw, arm);
+
+    return result;
+
+}
+
+
+/******************************************************************************
+*                                                                             *
+*  Paramètres  : raw = donnée brute de 16 bits à désassembler.                *
+*                arm = précise si l'encodage est en mode ARM ou Thumb.        *
+*                                                                             *
+*  Description : Désassemble une instruction ARMv7 liées au chapitre A7.4.3.  *
+*                                                                             *
+*  Retour      : Instruction mise en place ou NULL en cas d'échec.            *
+*                                                                             *
+*  Remarques   : -                                                            *
+*                                                                             *
+******************************************************************************/
+
+static GArchInstruction *process_armv7_simd_two_registers_and_a_scalar(uint32_t raw, bool arm)
+{
+    GArchInstruction *result;               /* Instruction à renvoyer      */
+    uint32_t u;                             /* Champ 'u' à retrouver       */
+    uint32_t a;                             /* Champ 'a' à retrouver       */
+
+    /**
+     * Suit les directives de :
+     * § A7.4.3 Two registers and a scalar
+     */
+
+    if (arm)
+    {
+        if ((raw & 0xfe800050) != 0xf2800040) return NULL;
+    }
+    else
+    {
+        if ((raw & 0xef800050) != 0xef800040) return NULL;
+    }
+
+    result = NULL;
+
+    if (arm)
+    {
+        u = (raw >> 24) & b1;
+        a = (raw >> 8) & b1111;
+    }
+    else
+    {
+        u = (raw >> 28) & b1;
+        a = (raw >> 8) & b1111;
+    }
+
+    if ((a & b1010) == b0000)
+        result = armv7_read_simd_instr_vmla_vmlal_vmls_vmlsl_by_scalar(raw, arm);
+
+    else if ((a & b1010) == b0010)
+        result = armv7_read_simd_instr_vmla_vmlal_vmls_vmlsl_by_scalar(raw, arm);
+
+    else if ((a & b1011) == b0011 && u == b0)
+        result = armv7_read_simd_instr_vqdmlal_vqdmlsl(raw, arm);
+
+    else if ((a & b1110) == b1000)
+        result = armv7_read_simd_instr_vmul_vmull_by_scalar(raw, arm);
+
+    else if (a == b1010)
+        result = armv7_read_simd_instr_vmul_vmull_by_scalar(raw, arm);
+
+    else if (a == b1011 && u == b0)
+        result = armv7_read_simd_instr_vqdmull(raw, arm);
+
+    else if (a == b1100)
+        result = armv7_read_simd_instr_vqdmulh(raw, arm);
+
+    else if (a == b1101)
+        result = armv7_read_simd_instr_vqrdmulh(raw, arm);
+
+    return result;
+
+}
+
+
+/******************************************************************************
+*                                                                             *
+*  Paramètres  : raw = donnée brute de 16 bits à désassembler.                *
+*                arm = précise si l'encodage est en mode ARM ou Thumb.        *
+*                                                                             *
+*  Description : Désassemble une instruction ARMv7 liées au chapitre A7.4.4.  *
+*                                                                             *
+*  Retour      : Instruction mise en place ou NULL en cas d'échec.            *
+*                                                                             *
+*  Remarques   : -                                                            *
+*                                                                             *
+******************************************************************************/
+
+static GArchInstruction *process_armv7_simd_two_registers_and_a_shift_amount(uint32_t raw, bool arm)
+{
+    GArchInstruction *result;               /* Instruction à renvoyer      */
+    uint32_t u;                             /* Champ 'u' à retrouver       */
+    uint32_t a;                             /* Champ 'a' à retrouver       */
+    uint32_t l;                             /* Champ 'l' à retrouver       */
+    uint32_t b;                             /* Champ 'b' à retrouver       */
+
+    /**
+     * Suit les directives de :
+     * § A7.4.4 Two registers and a shift amount
+     */
+
+    if (arm)
+    {
+        if ((raw & 0xfe800010) != 0xf2800010) return NULL;
+    }
+    else
+    {
+        if ((raw & 0xef800010) != 0xef800010) return NULL;
+    }
+
+    result = NULL;
+
+    if (arm)
+    {
+        u = (raw >> 24) & b1;
+        a = (raw >> 8) & b1111;
+        l = (raw >> 7) & b1;
+        b = (raw >> 6) & b1;
+    }
+    else
+    {
+        u = (raw >> 28) & b1;
+        a = (raw >> 8) & b1111;
+        l = (raw >> 7) & b1;
+        b = (raw >> 6) & b1;
+    }
+
+    if (a == b0000)
+        result = armv7_read_simd_instr_vshr(raw, arm);
+
+    else if (a == b0001)
+        result = armv7_read_simd_instr_vsra(raw, arm);
+
+    else if (a == b0010)
+        result = armv7_read_simd_instr_vrshr(raw, arm);
+
+    else if (a == b0011)
+        result = armv7_read_simd_instr_vrsra(raw, arm);
+
+    else if (a == b0100 && u == b1)
+        result = armv7_read_simd_instr_vsri(raw, arm);
+
+    else if (a == b0101)
+    {
+        if (u == b0)
+            result = armv7_read_simd_instr_vshl_immediate(raw, arm);
+
+        else/* if (u == b1)*/
+            result = armv7_read_simd_instr_vsli(raw, arm);
+
+    }
+
+    else if ((a & b1110) == b0110)
+        result = armv7_read_simd_instr_vqshl_vqshlu_immediate(raw, arm);
+
+    else if (a == b1000)
+    {
+        if (u == b0)
+        {
+            if (b == b0 && l == b0)
+                result = armv7_read_simd_instr_vshrn(raw, arm);
+
+            else if (b == b1 && l == b0)
+                result = armv7_read_simd_instr_vrshrn(raw, arm);
+
+        }
+        else/* if (u == b1)*/
+        {
+            if (b == b0 && l == b0)
+                result = armv7_read_simd_instr_vqshrn_vqshrun(raw, arm);
+
+            else if (b == b1 && l == b0)
+                result = armv7_read_simd_instr_vqrshrn_vqrshrun(raw, arm);
+
+        }
+
+    }
+
+    else if (a == b1001)
+    {
+        if (b == b0 && l == b0)
+            result = armv7_read_simd_instr_vqshrn_vqshrun(raw, arm);
+
+        else if (b == b1 && l == b0)
+            result = armv7_read_simd_instr_vqrshrn_vqrshrun(raw, arm);
+
+    }
+
+    else if (a == b1010 && b == b0 && l == b0)
+    {
+        result = armv7_read_simd_instr_vshll(raw, arm);
+
+        /* ??? */
+        if (result == NULL)
+            result = armv7_read_simd_instr_vmovl(raw, arm);
+
+    }
+
+    else if ((a & b1110) == b1110 && l == b0)
+        result = armv7_read_simd_instr_vcvt_between_floating_point_and_fixed_point_advanced_simd(raw, arm);
+
+    return result;
+
+}
+
+
+/******************************************************************************
+*                                                                             *
+*  Paramètres  : raw = donnée brute de 16 bits à désassembler.                *
+*                arm = précise si l'encodage est en mode ARM ou Thumb.        *
+*                                                                             *
+*  Description : Désassemble une instruction ARMv7 liées au chapitre A7.4.5.  *
+*                                                                             *
+*  Retour      : Instruction mise en place ou NULL en cas d'échec.            *
+*                                                                             *
+*  Remarques   : -                                                            *
+*                                                                             *
+******************************************************************************/
+
+static GArchInstruction *process_armv7_simd_two_registers_miscellaneous(uint32_t raw, bool arm)
+{
+    GArchInstruction *result;               /* Instruction à renvoyer      */
+    uint32_t a;                             /* Champ 'a' à retrouver       */
+    uint32_t b;                             /* Champ 'b' à retrouver       */
+
+    /**
+     * Suit les directives de :
+     * § A7.4.5 Two registers, miscellaneous
+     */
+
+    if (arm)
+    {
+        if ((raw & 0xffb00810) != 0xf3b00000) return NULL;
+    }
+    else
+    {
+        if ((raw & 0xffb00810) != 0xffb00000) return NULL;
+    }
+
+    result = NULL;
+
+    a = (raw >> 16) & b11;
+    b = (raw >> 6) & b11111;
+
+    if (a == b00)
+    {
+        if ((b & b11110) == b00000)
+            result = armv7_read_simd_instr_vrev16_vrev32_vrev64(raw, arm);
+
+        else if ((b & b11110) == b00010)
+            result = armv7_read_simd_instr_vrev16_vrev32_vrev64(raw, arm);
+
+        else if ((b & b11110) == b00100)
+            result = armv7_read_simd_instr_vrev16_vrev32_vrev64(raw, arm);
+
+        else if ((b & b11100) == b01000)
+            result = armv7_read_simd_instr_vpaddl(raw, arm);
+
+        else if ((b & b11110) == b10000)
+            result = armv7_read_simd_instr_vcls(raw, arm);
+
+        else if ((b & b11110) == b10010)
+            result = armv7_read_simd_instr_vclz(raw, arm);
+
+        else if ((b & b11110) == b10100)
+            result = armv7_read_simd_instr_vcnt(raw, arm);
+
+        else if ((b & b11110) == b10110)
+            result = armv7_read_simd_instr_vmvn_register(raw, arm);
+
+        else if ((b & b11100) == b11000)
+            result = armv7_read_simd_instr_vpadal(raw, arm);
+
+        else if ((b & b11110) == b11100)
+            result = armv7_read_simd_instr_vqabs(raw, arm);
+
+        else if ((b & b11110) == b11110)
+            result = armv7_read_simd_instr_vqneg(raw, arm);
+
+    }
+
+    else if (a == b01)
+    {
+        if ((b & b01110) == b00000)
+            result = armv7_read_simd_instr_vcgt_immediate_0(raw, arm);
+
+        else if ((b & b01110) == b00010)
+            result = armv7_read_simd_instr_vcge_immediate_0(raw, arm);
+
+        else if ((b & b01110) == b00100)
+            result = armv7_read_simd_instr_vceq_immediate_0(raw, arm);
+
+        else if ((b & b01110) == b00110)
+            result = armv7_read_simd_instr_vcle_immediate_0(raw, arm);
+
+        else if ((b & b01110) == b01000)
+            result = armv7_read_simd_instr_vclt_immediate_0(raw, arm);
+
+        else if ((b & b01110) == b01100)
+            result = armv7_read_simd_instr_vabs(raw, arm);
+
+        else if ((b & b01110) == b01110)
+            result = armv7_read_simd_instr_vneg(raw, arm);
+
+    }
+
+    return result;
+
+}
+
+
+/******************************************************************************
+*                                                                             *
+*  Paramètres  : raw = donnée brute de 16 bits à désassembler.                *
+*                arm = précise si l'encodage est en mode ARM ou Thumb.        *
+*                                                                             *
+*  Description : Désassemble une instruction ARMv7 liées au chapitre A7.4.6.  *
+*                                                                             *
+*  Retour      : Instruction mise en place ou NULL en cas d'échec.            *
+*                                                                             *
+*  Remarques   : -                                                            *
+*                                                                             *
+******************************************************************************/
+
+static GArchInstruction *process_armv7_simd_one_register_and_a_modified_immediate_value(uint32_t raw, bool arm)
+{
+    GArchInstruction *result;               /* Instruction à renvoyer      */
+    uint32_t cmode;                         /* Champ 'cmode' à retrouver   */
+    uint32_t op;                            /* Champ 'op' à retrouver      */
+
+    /**
+     * Suit les directives de :
+     * § A7.4.6 One register and a modified immediate value
+     */
+
+    if (arm)
+    {
+        if ((raw & 0xfeb80090) != 0xf2800010) return NULL;
+    }
+    else
+    {
+        if ((raw & 0xefb80090) != 0xef800010) return NULL;
+    }
+
+    result = NULL;
+
+    cmode = (raw >> 8) & b1111;
+    op = (raw >> 5) & b1;
+
+    if (op == b0)
+    {
+        if ((cmode & b1001) == b0000)
+            result = armv7_read_simd_instr_vmov_immediate(raw, arm);
+
+        else if ((cmode & b1001) == b0001)
+            result = armv7_read_simd_instr_vorr_immediate(raw, arm);
+
+        else if ((cmode & b1101) == b1000)
+            result = armv7_read_simd_instr_vmov_immediate(raw, arm);
+
+        else if ((cmode & b1101) == b1001)
+            result = armv7_read_simd_instr_vorr_immediate(raw, arm);
+
+        else if ((cmode & b1100) == b1100)
+            result = armv7_read_simd_instr_vmov_immediate(raw, arm);
+
+    }
+
+    else/* if (op == b1)*/
+    {
+        if ((cmode & b1001) == b0000)
+            result = armv7_read_simd_instr_vmvn_immediate(raw, arm);
+
+        else if ((cmode & b1001) == b0001)
+            result = armv7_read_simd_instr_vbic_immediate(raw, arm);
+
+        else if ((cmode & b1101) == b1000)
+            result = armv7_read_simd_instr_vmvn_immediate(raw, arm);
+
+        else if ((cmode & b1101) == b1001)
+            result = armv7_read_simd_instr_vbic_immediate(raw, arm);
+
+        else if ((cmode & b1110) == b1100)
+            result = armv7_read_simd_instr_vmvn_immediate(raw, arm);
+
+        else if (cmode == b1110)
+            result = armv7_read_simd_instr_vmov_immediate(raw, arm);
+
+        else if (cmode == b1111)
+            result = g_undef_instruction_new(IBS_UNDEFINED);
+
+    }
+
+    return result;
+
+}
+
+
+/******************************************************************************
+*                                                                             *
+*  Paramètres  : raw = donnée brute de 16 bits à désassembler.                *
+*                arm = précise si l'encodage est en mode ARM ou Thumb.        *
+*                                                                             *
+*  Description : Désassemble une instruction ARMv7 liées au chapitre A7.5.    *
+*                                                                             *
+*  Retour      : Instruction mise en place ou NULL en cas d'échec.            *
+*                                                                             *
+*  Remarques   : -                                                            *
+*                                                                             *
+******************************************************************************/
+
+GArchInstruction *process_armv7_simd_floating_point_data_processing_instructions(uint32_t raw, bool arm)
+{
+    GArchInstruction *result;               /* Instruction à renvoyer      */
+    uint32_t opc1;                          /* Champ 'opc1' à retrouver    */
+    uint32_t opc2;                          /* Champ 'opc2' à retrouver    */
+    uint32_t opc3;                          /* Champ 'opc3' à retrouver    */
+
+    /**
+     * Suit les directives de :
+     * § A7.5 Floating-point data-processing instructions
+     */
+
+    if (arm)
+    {
+        if ((raw & 0x0f000e10) != 0xee000a00) return NULL;
+    }
+    else
+    {
+        if ((raw & 0xef000e10) != 0x0e000a00) return NULL;
+    }
+
+    result = NULL;
+
+    opc1 = (raw >> 20) & b1111;
+    opc2 = (raw >> 16) & b1111;
+    opc3 = (raw >> 6) & b11;
+
+
+    if ((opc1 & b1011) == b0000)
+        result = armv7_read_simd_instr_vmla_vmls_floating_point(raw, arm);
+
+    else if ((opc1 & b1011) == b0001)
+        result = armv7_read_simd_instr_vnmla_vnmls_vnmul(raw, arm);
+
+    else if ((opc1 & b1011) == b0010)
+    {
+        if ((opc3 & b01) == b01)
+            result = armv7_read_simd_instr_vnmla_vnmls_vnmul(raw, arm);
+
+        else/* if ((opc3 & b01) == b00)*/
+            result = armv7_read_simd_instr_vmul_floating_point(raw, arm);
+
+    }
+
+    else if ((opc1 & b1011) == b0011)
+    {
+        if ((opc3 & b01) == b00)
+            result = armv7_read_simd_instr_vadd_floating_point(raw, arm);
+
+        else/* if ((opc3 & b01) == b01)*/
+            result = armv7_read_simd_instr_vsub_floating_point(raw, arm);
+
+    }
+
+    else if ((opc1 & b1011) == b1000)
+    {
+        if ((opc3 & b01) == b00)
+            result = armv7_read_simd_instr_vdiv(raw, arm);
+
+    }
+
+    else if ((opc1 & b1011) == b1001)
+        result = armv7_read_simd_instr_vfnma_vfnms(raw, arm);
+
+    else if ((opc1 & b1011) == b1010)
+        result = armv7_read_simd_instr_vfma_vfms(raw, arm);
+
+    else if ((opc1 & b1011) == b1011)
+    {
+        if ((opc3 & b01) == b00)
+            result = armv7_read_simd_instr_vmov_immediate(raw, arm);
+
+        else if (opc2 == b0000)
+        {
+            if (opc3 == b01)
+                result = armv7_read_simd_instr_vmov_register(raw, arm);
+
+            else if (opc3 == b11)
+                result = armv7_read_simd_instr_vabs(raw, arm);
+
+        }
+
+        else if (opc2 == b0001)
+        {
+            if (opc3 == b01)
+                result = armv7_read_simd_instr_vneg(raw, arm);
+
+            else if (opc3 == b11)
+                result = armv7_read_simd_instr_vsqrt(raw, arm);
+
+        }
+
+        else if ((opc2 & b1110) == b0010 && (opc3 & b01) == b01)
+                result = armv7_read_simd_instr_vcvtb_vcvtt(raw, arm);
+
+        else if ((opc2 & b1110) == b0100 && (opc3 & b01) == b01)
+                result = armv7_read_simd_instr_vcmp_vcmpe(raw, arm);
+
+        else if (opc2 == b0111 && opc3 == b11)
+                result = armv7_read_simd_instr_vcvt_between_double_precision_and_single_precision(raw, arm);
+
+        else if (opc2 == b1000 && (opc3 & b01) == b01)
+                result = armv7_read_simd_instr_vcvt_vcvtr_between_floating_point_and_integer_floating_point(raw, arm);
+
+        else if ((opc2 & b1110) == b1010 && (opc3 & b01) == b01)
+                result = armv7_read_simd_instr_vcvt_between_floating_point_and_fixed_point_floating_point(raw, arm);
+
+        else if ((opc2 & b1110) == b1100 && (opc3 & b01) == b01)
+                result = armv7_read_simd_instr_vcvt_vcvtr_between_floating_point_and_integer_floating_point(raw, arm);
+
+        else if ((opc2 & b1110) == b1110 && (opc3 & b01) == b01)
+                result = armv7_read_simd_instr_vcvt_between_floating_point_and_fixed_point_floating_point(raw, arm);
+
+    }
+
+    return result;
+
+}
+
+
+/******************************************************************************
+*                                                                             *
+*  Paramètres  : raw = donnée brute de 16 bits à désassembler.                *
+*                arm = précise si l'encodage est en mode ARM ou Thumb.        *
+*                                                                             *
+*  Description : Désassemble une instruction ARMv7 liées au chapitre A7.6.    *
+*                                                                             *
+*  Retour      : Instruction mise en place ou NULL en cas d'échec.            *
+*                                                                             *
+*  Remarques   : -                                                            *
+*                                                                             *
+******************************************************************************/
+
+GArchInstruction *process_armv7_simd_extension_register_load_store_instructions(uint32_t raw, bool arm)
+{
+    GArchInstruction *result;               /* Instruction à renvoyer      */
+    uint32_t opcode;                        /* Champ 'opcode' à retrouver  */
+    uint32_t rn;                            /* Champ 'rn' à retrouver      */
+
+    /**
+     * Suit les directives de :
+     * § A7.6 Extension register load/store instructions
+     */
+
+    if (arm)
+    {
+        if ((raw & 0x0e000e00) != 0x0c000a00) return NULL;
+    }
+    else
+    {
+        if ((raw & 0xee000e00) != 0xec000a00) return NULL;
+    }
+
+    result = NULL;
+
+    opcode = (raw >> 20) & b11111;
+    rn = (raw >> 16) & b1111;
+
+    if ((opcode & b11110) == b00100)
+        result = process_armv7_simd_64_bit_transfers_between_arm_core_and_extension_registers(raw, arm);
+
+    else if ((opcode & b11011) == b01000)
+        result = armv7_read_simd_instr_vstm(raw, arm);
+
+    else if ((opcode & b11011) == b01010)
+        result = armv7_read_simd_instr_vstm(raw, arm);
+
+    else if ((opcode & b10011) == b10000)
+        result = armv7_read_simd_instr_vstr(raw, arm);
+
+    else if ((opcode & b11011) == b10010)
+    {
+        if (rn != b1101)
+            result = armv7_read_simd_instr_vstm(raw, arm);
+
+        else/* if (rn == b1101)*/
+            result = armv7_read_simd_instr_vpush(raw, arm);
+
+    }
+
+    else if ((opcode & b11011) == b01001)
+        result = armv7_read_simd_instr_vldm(raw, arm);
+
+    else if ((opcode & b11011) == b01011)
+    {
+        if (rn != 1101)
+            result = armv7_read_simd_instr_vldm(raw, arm);
+
+        else/* if (rn == 1101)*/
+            result = armv7_read_simd_instr_vpop(raw, arm);
+
+    }
+
+    else if ((opcode & b10011) == b10001)
+        result = armv7_read_simd_instr_vldr(raw, arm);
+
+    else if ((opcode & b11011) == b10011)
+        result = armv7_read_simd_instr_vldm(raw, arm);
+
+    return result;
+
+}
+
+
+/******************************************************************************
+*                                                                             *
+*  Paramètres  : raw = donnée brute de 16 bits à désassembler.                *
+*                arm = précise si l'encodage est en mode ARM ou Thumb.        *
+*                                                                             *
+*  Description : Désassemble une instruction ARMv7 liées au chapitre A7.7.    *
+*                                                                             *
+*  Retour      : Instruction mise en place ou NULL en cas d'échec.            *
+*                                                                             *
+*  Remarques   : -                                                            *
+*                                                                             *
+******************************************************************************/
+
+GArchInstruction *process_armv7_simd_advanced_simd_element_or_structure_load_store_instructions(uint32_t raw, bool arm)
+{
+    GArchInstruction *result;               /* Instruction à renvoyer      */
+    uint32_t a;                             /* Champ 'a' à retrouver       */
+    uint32_t l;                             /* Champ 'l' à retrouver       */
+    uint32_t b;                             /* Champ 'b' à retrouver       */
+
+    /**
+     * Suit les directives de :
+     * § A7.7 Advanced SIMD element or structure load/store instructions
+     */
+
+    if (arm)
+    {
+        if ((raw & 0xff100000) != 0xf4000000) return NULL;
+    }
+    else
+    {
+        if ((raw & 0xff100000) != 0xf9000000) return NULL;
+    }
+
+    result = NULL;
+
+    a = (raw >> 23) & b1;
+    l = (raw >> 21) & b1;
+    b = (raw >> 8) & b1111;
+
+    if (l == b0)
+    {
+        if (a == b0)
+        {
+            if (b == b0010)
+                result = armv7_read_simd_instr_vst1_multiple_single_elements(raw, arm);
+
+            else if ((b & b1110) == b0110)
+                result = armv7_read_simd_instr_vst1_multiple_single_elements(raw, arm);
+
+            else if (b == b1010)
+                result = armv7_read_simd_instr_vst1_multiple_single_elements(raw, arm);
+
+            else if (b == b0011)
+                result = armv7_read_simd_instr_vst2_multiple_2_element_structures(raw, arm);
+
+            else if ((b & b1110) == b1000)
+                result = armv7_read_simd_instr_vst2_multiple_2_element_structures(raw, arm);
+
+            else if ((b & b1110) == b0100)
+                result = armv7_read_simd_instr_vst3_multiple_3_element_structures(raw, arm);
+
+            else if ((b & b1110) == b0000)
+                result = armv7_read_simd_instr_vst4_multiple_4_element_structures(raw, arm);
+
+        }
+
+        else/* if (a == b1)*/
+        {
+            if ((b & b1011) == b0000)
+                result = armv7_read_simd_instr_vst1_single_element_from_one_lane(raw, arm);
+
+            else if (b == b1000)
+                result = armv7_read_simd_instr_vst1_single_element_from_one_lane(raw, arm);
+
+            else if ((b & b1011) == b0001)
+                result = armv7_read_simd_instr_vst2_single_2_element_structure_from_one_lane(raw, arm);
+
+            else if (b == b1001)
+                result = armv7_read_simd_instr_vst2_single_2_element_structure_from_one_lane(raw, arm);
+
+            else if ((b & b1011) == b0010)
+                result = armv7_read_simd_instr_vst3_single_3_element_structure_from_one_lane(raw, arm);
+
+            else if (b == b1010)
+                result = armv7_read_simd_instr_vst3_single_3_element_structure_from_one_lane(raw, arm);
+
+            else if ((b & b1011) == b0011)
+                result = armv7_read_simd_instr_vst4_single_4_element_structure_from_one_lane(raw, arm);
+
+            else if (b == b1011)
+                result = armv7_read_simd_instr_vst4_single_4_element_structure_from_one_lane(raw, arm);
+
+        }
+
+    }
+
+    else/* if (l == b1)*/
+    {
+        if (a == b0)
+        {
+            if (b == b0010)
+                result = armv7_read_simd_instr_vld1_multiple_single_elements(raw, arm);
+
+            else if ((b & b1110) == b0110)
+                result = armv7_read_simd_instr_vld1_multiple_single_elements(raw, arm);
+
+            else if (b == b1010)
+                result = armv7_read_simd_instr_vld1_multiple_single_elements(raw, arm);
+
+            else if (b == b0011)
+                result = armv7_read_simd_instr_vld2_multiple_2_element_structures(raw, arm);
+
+            else if ((b & b1110) == b1000)
+                result = armv7_read_simd_instr_vld2_multiple_2_element_structures(raw, arm);
+
+            else if ((b & b1110) == b0100)
+                result = armv7_read_simd_instr_vld3_multiple_3_element_structures(raw, arm);
+
+            else if ((b & b1110) == b0000)
+                result = armv7_read_simd_instr_vld4_multiple_4_element_structures(raw, arm);
+
+        }
+
+        else/* if (a == b1)*/
+        {
+            if ((b & b1011) == b0000)
+                result = armv7_read_simd_instr_vld1_single_element_to_one_lane(raw, arm);
+
+            else if (b == b1000)
+                result = armv7_read_simd_instr_vld1_single_element_to_one_lane(raw, arm);
+
+            else if (b == b1100)
+                result = armv7_read_simd_instr_vld1_single_element_to_all_lanes(raw, arm);
+
+            else if ((b & b1011) == b0001)
+                result = armv7_read_simd_instr_vld2_single_2_element_structure_to_one_lane(raw, arm);
+
+            else if (b == b1001)
+                result = armv7_read_simd_instr_vld2_single_2_element_structure_to_one_lane(raw, arm);
+
+            else if (b == b1101)
+                result = armv7_read_simd_instr_vld2_single_2_element_structure_to_all_lanes(raw, arm);
+
+            else if ((b & b1011) == b0010)
+                result = armv7_read_simd_instr_vld3_single_3_element_structure_to_one_lane(raw, arm);
+
+            else if (b == b1010)
+                result = armv7_read_simd_instr_vld3_single_3_element_structure_to_one_lane(raw, arm);
+
+            else if (b == b1110)
+                result = armv7_read_simd_instr_vld3_single_3_element_structure_to_all_lanes(raw, arm);
+
+            else if ((b & b1011) == b0011)
+                result = armv7_read_simd_instr_vld4_single_4_element_structure_to_one_lane(raw, arm);
+
+            else if (b == b1011)
+                result = armv7_read_simd_instr_vld4_single_4_element_structure_to_one_lane(raw, arm);
+
+            else if (b == b1111)
+                result = armv7_read_simd_instr_vld4_single_4_element_structure_to_all_lanes(raw, arm);
+
+        }
+
+    }
+
+    return result;
+
+}
+
+
+/******************************************************************************
+*                                                                             *
+*  Paramètres  : raw = donnée brute de 16 bits à désassembler.                *
+*                arm = précise si l'encodage est en mode ARM ou Thumb.        *
+*                                                                             *
+*  Description : Désassemble une instruction ARMv7 liées au chapitre A7.8.    *
+*                                                                             *
+*  Retour      : Instruction mise en place ou NULL en cas d'échec.            *
+*                                                                             *
+*  Remarques   : -                                                            *
+*                                                                             *
+******************************************************************************/
+
+GArchInstruction *process_armv7_simd_8_16_and_32_bit_transfer_between_arm_core_and_extension_registers(uint32_t raw, bool arm)
+{
+    GArchInstruction *result;               /* Instruction à renvoyer      */
+    uint32_t a;                             /* Champ 'a' à retrouver       */
+    uint32_t l;                             /* Champ 'l' à retrouver       */
+    uint32_t c;                             /* Champ 'c' à retrouver       */
+    uint32_t b;                             /* Champ 'b' à retrouver       */
+
+    /**
+     * Suit les directives de :
+     * § A7.8 8, 16, and 32-bit transfer between ARM core and extension registers
+     */
+
+    if (arm)
+    {
+        if ((raw & 0x0f000e10) != 0x0e000a10) return NULL;
+    }
+    else
+    {
+        if ((raw & 0xef000e10) != 0xee000a10) return NULL;
+    }
+
+    result = NULL;
+
+    a = (raw >> 21) & b111;
+    l = (raw >> 20) & b1;
+    c = (raw >> 8) & b1;
+    b = (raw >> 5) & b11;
+
+    if (l == b0)
+    {
+        if (c == b0)
+        {
+            if (a == b000)
+                result = armv7_read_simd_instr_vmov_between_arm_core_register_and_single_precision_register(raw, arm);
+
+            else if (a == b111)
+            {
+                result = armv7_read_simd_instr_vmsr(raw, arm);
+
+                if (result == NULL /* ! */)
+                    result = armv7_read_simd_instr_vmsr_b9(raw, arm);
+
+            }
+
+        }
+
+        else/* if (c == b1)*/
+        {
+            if ((a & b100) == b000)
+                result = armv7_read_simd_instr_vmov_arm_core_register_to_scalar(raw, arm);
+
+            else if (/*(a & b100) == b000) && */(b & b10) == b00)
+                result = armv7_read_simd_instr_vdup_arm_core_register(raw, arm);
+
+        }
+
+    }
+
+    else/* if (l == b1)*/
+    {
+        if (c == b0)
+        {
+            if (a == b000)
+                result = armv7_read_simd_instr_vmov_between_arm_core_register_and_single_precision_register(raw, arm);
+
+            else if (a == b111)
+            {
+                result = armv7_read_simd_instr_vmrs(raw, arm);
+
+                if (result == NULL /* ! */)
+                    result = armv7_read_simd_instr_vmrs_b9(raw, arm);
+
+            }
+
+        }
+
+        else/* if (c == b1)*/
+            result = armv7_read_simd_instr_vmov_scalar_to_arm_core_register(raw, arm);
+
+    }
+
+    return result;
+
+}
+
+
+/******************************************************************************
+*                                                                             *
+*  Paramètres  : raw = donnée brute de 16 bits à désassembler.                *
+*                arm = précise si l'encodage est en mode ARM ou Thumb.        *
+*                                                                             *
+*  Description : Désassemble une instruction ARMv7 liées au chapitre A7.9.    *
+*                                                                             *
+*  Retour      : Instruction mise en place ou NULL en cas d'échec.            *
+*                                                                             *
+*  Remarques   : -                                                            *
+*                                                                             *
+******************************************************************************/
+
+GArchInstruction *process_armv7_simd_64_bit_transfers_between_arm_core_and_extension_registers(uint32_t raw, bool arm)
+{
+    GArchInstruction *result;               /* Instruction à renvoyer      */
+    uint32_t c;                             /* Champ 'c' à retrouver       */
+    uint32_t op;                            /* Champ 'op' à retrouver      */
+
+    /**
+     * Suit les directives de :
+     * § A7.9 64-bit transfers between ARM core and extension registers
+     */
+
+    if (arm)
+    {
+        if ((raw & 0x0fe00e00) != 0x0c400a00) return NULL;
+    }
+    else
+    {
+        if ((raw & 0xefe00e00) != 0xec400a00) return NULL;
+    }
+
+    result = NULL;
+
+    c = (raw >> 8) & b1;
+    op = (raw >> 4) & b1111;
+
+    if (c == b0 && (op & b1101) == 0001)
+        result = armv7_read_simd_instr_vmov_between_two_arm_core_registers_and_two_single_precision_registers(raw, arm);
+
+    else if (c == b1 && (op & b1101) == 0001)
+        result = armv7_read_simd_instr_vmov_between_two_arm_core_registers_and_a_doubleword_extension_register(raw, arm);
+
+    return result;
+
+}
diff --git a/src/arch/arm/v7/simd.h b/src/arch/arm/v7/simd.h
new file mode 100644
index 0000000..a7894c1
--- /dev/null
+++ b/src/arch/arm/v7/simd.h
@@ -0,0 +1,55 @@
+
+/* Chrysalide - Outil d'analyse de fichiers binaires
+ * simd.h - prototypes pour le désassemblage des instructions ARMv7 SIMD
+ *
+ * Copyright (C) 2016 Cyrille Bagard
+ *
+ *  This file is part of Chrysalide.
+ *
+ *  OpenIDA is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 3 of the License, or
+ *  (at your option) any later version.
+ *
+ *  OpenIDA is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Foobar.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+#ifndef _ARCH_ARM_V7_SIMD_H
+#define _ARCH_ARM_V7_SIMD_H
+
+
+#include <stdbool.h>
+
+
+#include "../../instruction.h"
+
+
+
+/* Désassemble une instruction ARMv7 liées au chapitre A7.4. */
+GArchInstruction *process_armv7_simd_advanced_simd_data_processing_instructions(uint32_t, bool);
+
+/* Désassemble une instruction ARMv7 liées au chapitre A7.5. */
+GArchInstruction *process_armv7_simd_floating_point_data_processing_instructions(uint32_t, bool);
+
+/* Désassemble une instruction ARMv7 liées au chapitre A7.6. */
+GArchInstruction *process_armv7_simd_extension_register_load_store_instructions(uint32_t, bool);
+
+/* Désassemble une instruction ARMv7 liées au chapitre A7.7. */
+GArchInstruction *process_armv7_simd_advanced_simd_element_or_structure_load_store_instructions(uint32_t, bool);
+
+/* Désassemble une instruction ARMv7 liées au chapitre A7.8. */
+GArchInstruction *process_armv7_simd_8_16_and_32_bit_transfer_between_arm_core_and_extension_registers(uint32_t, bool);
+
+/* Désassemble une instruction ARMv7 liées au chapitre A7.9. */
+GArchInstruction *process_armv7_simd_64_bit_transfers_between_arm_core_and_extension_registers(uint32_t, bool);
+
+
+
+#endif  /* _ARCH_ARM_V7_SIMD_H */
diff --git a/src/arch/arm/v7/thumb_32.c b/src/arch/arm/v7/thumb_32.c
index 9dbad13..7f6ae74 100644
--- a/src/arch/arm/v7/thumb_32.c
+++ b/src/arch/arm/v7/thumb_32.c
@@ -24,10 +24,10 @@
 #include "thumb_32.h"
 
 
-#include <assert.h>
 #include <stdint.h>
 
 
+#include "simd.h"
 #include "opcodes/thumb_32_opcodes.h"
 #include "opcodes/opcodes_tmp_thumb_32.h"
 #include "../../undefined.h"
@@ -182,9 +182,7 @@ GArchInstruction *process_armv7_thumb_32_instruction_set_encoding(uint32_t raw)
                 result = g_undef_instruction_new(IBS_UNDEFINED);
 
             else if ((op2 & b1110001) == b0010000)
-                /* Advanced SIMD element or structure load/store instructions on page A7-275 */
-                /*result = process_armv7_thumb_32_advanced_simd_element_or_structure_load_store_instructions(raw);*/
-                assert(false);
+                result = process_armv7_simd_advanced_simd_element_or_structure_load_store_instructions(raw, false);
 
             else if ((op2 & b1110000) == b0100000)
                 result = process_armv7_thumb_32_data_processing_register(raw);
@@ -988,8 +986,7 @@ static GArchInstruction *process_armv7_thumb_32_load_halfword_memory_hints(uint3
                 result = armv7_read_thumb_32_instr_ldrsh_literal(raw);
 
             else/* if (rt == b1111)*/
-                /* Unallocated memory hint (treat as NOP) */
-                assert(false);
+                result = g_undef_instruction_new(IBS_NOP);
 
         }
 
@@ -1044,12 +1041,10 @@ static GArchInstruction *process_armv7_thumb_32_load_halfword_memory_hints(uint3
                 result = armv7_read_thumb_32_instr_ldrsht(raw);
 
             else if (op2 == b000000 && rt == b1111)
-                /* Unallocated memory hint (treat as NOP) */
-                assert(false);
+                result = g_undef_instruction_new(IBS_NOP);
 
             else if ((op2 & b111100) == b110000 && rt == b1111)
-                /* Unallocated memory hint (treat as NOP) */
-                assert(false);
+                result = g_undef_instruction_new(IBS_NOP);
 
         }
 
@@ -1059,8 +1054,7 @@ static GArchInstruction *process_armv7_thumb_32_load_halfword_memory_hints(uint3
                 result = armv7_read_thumb_32_instr_ldrsh_immediate(raw);
 
             else/* if (rt == b1111)*/
-                /* Unallocated memory hint (treat as NOP) */
-                assert(false);
+                result = g_undef_instruction_new(IBS_NOP);
 
         }
 
@@ -2215,8 +2209,7 @@ static GArchInstruction *process_armv7_thumb_32_coprocessor_advanced_simd_and_fl
         result = g_undef_instruction_new(IBS_UNDEFINED);
 
     else if ((op1 & b110000) == b110000)
-        /* Advanced SIMD data-processing instructions on page A7-261 */
-        assert(false);
+        result = process_armv7_simd_advanced_simd_data_processing_instructions(raw, false);
 
     else if ((coproc & b1110) != b1010)
     {
@@ -2253,22 +2246,18 @@ static GArchInstruction *process_armv7_thumb_32_coprocessor_advanced_simd_and_fl
     else if ((coproc & b1110) == b1010)
     {
         if ((op1 & b100000) == b000000 && (op1 & b111010) != b000000)
-            /* Extension register load/store instructions on page A7-274 */
-            assert(false);
+            result = process_armv7_simd_extension_register_load_store_instructions(raw, false);
 
         else if ((op1 & b111110) == b000100)
-            /* 64-bit transfers between ARM core and extension registers on page A7-279 */
-            assert(false);
+            result = process_armv7_simd_64_bit_transfers_between_arm_core_and_extension_registers(raw, false);
 
         else if ((op1 & b110000) == b100000)
         {
             if (op == b0)
-                /* Floating-point data-processing instructions on page A7-272 */
-                assert(false);
+                result = process_armv7_simd_floating_point_data_processing_instructions(raw, false);
 
             else/* if (op == b1)*/
-                /* 8, 16, and 32-bit transfer between ARM core and extension registers on page A7-278 */
-                assert(false);
+                result = process_armv7_simd_8_16_and_32_bit_transfer_between_arm_core_and_extension_registers(raw, false);
 
         }