Supported a new architecture (MIPS).

git-svn-id: svn://svn.gna.org/svn/chrysalide/trunk@67 abbe820e-26c8-41b2-8c08-b7b2b41f8b0a

1 files changed, 105 insertions, 0 deletions

diff --git a/src/arch/mips/instruction.h b/src/arch/mips/instruction.h
new file mode 100644
index 0000000..79b63f9
--- /dev/null
+++ b/src/arch/mips/instruction.h
@@ -0,0 +1,105 @@
+
+/* OpenIDA - Outil d'analyse de fichiers binaires
+ * instruction.h - prototypes pour la gestion des instructions de l'architecture MIPS
+ *
+ * Copyright (C) 2008 Cyrille Bagard
+ *
+ *  This file is part of OpenIDA.
+ *
+ *  OpenIDA is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 3 of the License, or
+ *  (at your option) any later version.
+ *
+ *  OpenIDA is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Foobar.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+#ifndef _ARCH_MIPS_INSTRUCTION_H
+#define _ARCH_MIPS_INSTRUCTION_H
+
+
+#include "../instruction.h"
+
+
+
+
+
+
+/* Enumération de tous les opcodes */
+typedef enum _MipsOpcodes
+{
+    MOP_NOP,                                /* nop (0x00 ... 0x00)         */
+
+    MOP_SRA,                                /* sra (0x00 ... 0x03)         */
+
+    MOP_JR,                                 /* jr (0x00 ... 0x08)          */
+    MOP_JALR,                               /* jalr (0x00 ... 0x09)        */
+    MOP_JALR_HB,                            /* jalr.hb (0x00 ... 0x09)     */
+
+
+    MOP_ADDU,                               /* addu (0x00 ... 0x21)        */
+    MOP_SUB,                                /* sub (0x00 ... 0x22)         */
+    MOP_SUBU,                               /* subu (0x00 ... 0x23)        */
+
+    MOP_AND,                                /* and (0x00 ... 0x24)         */
+
+    MOP_BGEZAL,                             /* bgezal (0x04 ... 0x11 ...)  */
+
+    MOP_BEQ,                                /* beq (0x10)                  */
+    MOP_BNE,                                /* bne (0x14)                  */
+
+    MOP_ADDIU,                              /* addiu (0x24)                */
+
+    MOP_BEQL,                               /* beql (0x50)                 */
+
+    MOP_LW,                                 /* lw (0x8c)                   */
+    MOP_LUI,                                /* lui (0x3c)                  */
+
+    MOP_LBU,                                /* lbu (0x90)                  */
+
+    MOP_SB,                                 /* sb (0xa0)                   */
+    MOP_SW,                                 /* sw (0xac)                   */
+
+    MOP_COUNT
+
+
+} MipsOpcodes;
+
+
+#define G_TYPE_MIPS_INSTRUCTION                 g_mips_instruction_get_type()
+#define G_MIPS_INSTRUCTION(obj)                 (G_TYPE_CHECK_INSTANCE_CAST((obj), g_mips_instruction_get_type(), GMipsInstruction))
+#define G_IS_MIPS_INSTRUCTION(obj)              (G_TYPE_CHECK_INSTANCE_TYPE((obj), g_mips_instruction_get_type()))
+#define G_MIPS_INSTRUCTION_GET_IFACE(inst)      (G_TYPE_INSTANCE_GET_INTERFACE((inst), g_mips_instruction_get_type(), GMipsInstructionIface))
+
+
+/* Définition générique d'une instruction d'architecture MIPS (instance) */
+typedef struct _GMipsInstruction GMipsInstruction;
+
+/* Définition générique d'une instruction d'architecture MIPS (classe) */
+typedef struct _GMipsInstructionClass GMipsInstructionClass;
+
+
+/* Indique le type défini pour une instruction d'architecture MIPS. */
+GType g_mips_instruction_get_type(void);
+
+/* Crée une instruction pour l'architecture MIPS. */
+GArchInstruction *g_mips_instruction_new(MipsOpcodes);
+
+
+
+/* --------------------- AIDE A LA MISE EN PLACE D'INSTRUCTIONS --------------------- */
+
+
+/* Recherche l'identifiant de la prochaine instruction. */
+MipsOpcodes mips_guess_next_instruction(const bin_t *, off_t, off_t);
+
+
+
+#endif  /* _ARCH_MIPS_INSTRUCTION_H */