diff options
| author | Cyrille Bagard <nocbos@gmail.com> | 2008-10-26 23:37:51 (GMT) |
|---|---|---|
| committer | Cyrille Bagard <nocbos@gmail.com> | 2008-10-26 23:37:51 (GMT) |
| commit | 197933fdf469ab9b8897b33c51809c128f1e3c03 (patch) | |
| tree | 104d91be1a69d80eb4b59b247e4b719531bc7492 /src/arch/x86/instruction.h | |
| parent | ac438e8ad47f267c9eb6f462eb5a7e2b5c017f26 (diff) | |
Completed support of the 0x81 and 0xc1 opcodes.
git-svn-id: svn://svn.gna.org/svn/chrysalide/trunk@37 abbe820e-26c8-41b2-8c08-b7b2b41f8b0a
Diffstat (limited to 'src/arch/x86/instruction.h')
| -rw-r--r-- | src/arch/x86/instruction.h | 28 |
1 files changed, 24 insertions, 4 deletions
diff --git a/src/arch/x86/instruction.h b/src/arch/x86/instruction.h index baf911d..1c97255 100644 --- a/src/arch/x86/instruction.h +++ b/src/arch/x86/instruction.h @@ -92,11 +92,17 @@ typedef enum _X86Opcodes X86_OP_JE_8, /* je (0x74) */ X86_OP_JNE_8, /* jne (0x75) */ - X86_OP_XOR_RM8_IMM8, /* xor (0x81 6) */ + X86_OP_XOR_RM8_IMM8, /* xor (0x80 6) */ X86_OP_CMP_RM8_IMM8, /* cmp (0x80 7) */ - X86_OP_ADD_RM1632_IMM1632, /* add ([0x66] 0x81 0) */ + X86_OP_ADD_RM1632_IMM1632, /* add ([0x66] 0x81 0) */ + X86_OP_OR_RM1632_IMM1632, /* or ([0x66] 0x81 1) */ + X86_OP_ADC_RM1632_IMM1632, /* adc ([0x66] 0x81 2) */ + X86_OP_SBB_RM1632_IMM1632, /* sbb ([0x66] 0x81 3) */ + X86_OP_AND_RM1632_IMM1632, /* and ([0x66] 0x81 4) */ + X86_OP_SUB_RM1632_IMM1632, /* sub ([0x66] 0x81 5) */ X86_OP_XOR_RM1632_IMM1632, /* xor ([0x66] 0x81 6) */ + X86_OP_CMP_RM1632_IMM1632, /* xor ([0x66] 0x81 7) */ X86_OP_ADD_RM1632_IMM8, /* add ([0x66] 0x83 0) */ X86_OP_OR_RM1632_IMM8, /* or ([0x66] 0x83 1) */ @@ -135,6 +141,13 @@ typedef enum _X86Opcodes X86_OP_MOV_E_SI, /* mov ([0x66] 0xbe) */ X86_OP_MOV_E_DI, /* mov ([0x66] 0xbf) */ + X86_OP_ROL_RM1632_IMM8, /* rol ([0x66 0xc1 0) */ + X86_OP_ROR_RM1632_IMM8, /* ror ([0x66 0xc1 1) */ + X86_OP_RCL_RM1632_IMM8, /* rcl ([0x66 0xc1 2) */ + X86_OP_RCR_RM1632_IMM8, /* rcr ([0x66 0xc1 3) */ + X86_OP_SHL_RM1632_IMM8, /* shl ([0x66 0xc1 4) */ + X86_OP_SHR_RM1632_IMM8, /* shr ([0x66 0xc1 5) */ + X86_OP_SAL_RM1632_IMM8, /* sal ([0x66 0xc1 6) */ X86_OP_SAR_RM1632_IMM8, /* sar ([0x66 0xc1 7) */ X86_OP_RET, /* ret (0xc3) */ @@ -157,6 +170,8 @@ typedef enum _X86Opcodes X86_OP_JMP_RM1632, /* jmp ([0x66] 0xff 4) */ X86_OP_PUSH_RM1632, /* push ([0x66] 0xff 6) */ + X86_OP_MOVZX_R1632_RM8, /* movzx ([0x66] 0x0f 0xb6) */ + X86_OP_COUNT } X86Opcodes; @@ -167,11 +182,16 @@ typedef enum _X86Opcodes /* Eventuel préfixe rencontré */ typedef enum _X86Prefix { - X86_PRE_NONE = 0, /* Aucun préfixe */ + X86_PRE_NONE = (0 << 0), /* Aucun préfixe */ + + + /* Groupe 3 */ + X86_PRE_OPSIZE = (1 << 1), /* Basculement des opérandes */ - X86_PRE_OPSIZE /* Basculement des opérandes */ + /* Autres */ + X86_PRE_ESCAPE = (1 << 3) /* Opcode sur deux octets */ } X86Prefix; |