diff options
| author | Cyrille Bagard <nocbos@gmail.com> | 2010-08-18 23:20:47 (GMT) |
|---|---|---|
| committer | Cyrille Bagard <nocbos@gmail.com> | 2010-08-18 23:20:47 (GMT) |
| commit | c0831e2a8d16d65e8f31e52a63b703086609d8dd (patch) | |
| tree | b5587b780da2b5da3fa84869431d6409e7eec782 /src/arch/x86/instruction.h | |
| parent | 9ed927a6b6405633a82f378438c533fd0112f16d (diff) | |
Supported several extra x86 instructions.
git-svn-id: svn://svn.gna.org/svn/chrysalide/trunk@182 abbe820e-26c8-41b2-8c08-b7b2b41f8b0a
Diffstat (limited to 'src/arch/x86/instruction.h')
| -rw-r--r-- | src/arch/x86/instruction.h | 53 |
1 files changed, 48 insertions, 5 deletions
diff --git a/src/arch/x86/instruction.h b/src/arch/x86/instruction.h index bd57ff6..001233e 100644 --- a/src/arch/x86/instruction.h +++ b/src/arch/x86/instruction.h @@ -78,7 +78,7 @@ typedef enum _X86Opcodes XOP_CMP_RM8_R8, /* cmp (0x38) */ XOP_CMP_RM1632_R1632, /* cmp ([0x66] 0x39) */ - + XOP_CMP_R8_RM8, /* cmp (0x3a) */ XOP_CMP_R1632_RM1632, /* cmp ([0x66] 0x3b) */ XOP_CMP_AL_IMM8, /* cmp (0x3c) */ XOP_CMP_E_AX_IMM1632, /* cmp ([0x66] 0x3d) */ @@ -232,8 +232,14 @@ typedef enum _X86Opcodes XOP_MOV_E_BP_IMM1632, /* mov ([0x66] 0xbd) */ XOP_MOV_E_SI_IMM1632, /* mov ([0x66] 0xbe) */ XOP_MOV_E_DI_IMM1632, /* mov ([0x66] 0xbf) */ - - + XOP_ROL_RM8_IMM8, /* rol (0xc0 0) */ + XOP_ROR_RM8_IMM8, /* ror (0xc0 1) */ + XOP_RCL_RM8_IMM8, /* rcl (0xc0 2) */ + XOP_RCR_RM8_IMM8, /* rcr (0xc0 3) */ + XOP_SHL_RM8_IMM8, /* shl (0xc0 4) */ + XOP_SHR_RM8_IMM8, /* shr (0xc0 5) */ + XOP_SAL_RM8_IMM8, /* sal (0xc0 6) */ + XOP_SAR_RM8_IMM8, /* sar (0xc0 7) */ XOP_ROL_RM1632_IMM8, /* rol ([0x66] 0xc1 0) */ XOP_ROR_RM1632_IMM8, /* ror ([0x66] 0xc1 1) */ XOP_RCL_RM1632_IMM8, /* rcl ([0x66] 0xc1 2) */ @@ -244,17 +250,52 @@ typedef enum _X86Opcodes XOP_SAR_RM1632_IMM8, /* sar ([0x66] 0xc1 7) */ - XOP_RET, /* ret (0xc3) */ + XOP_RETN_IMM16, /* retn (0xc2) */ + XOP_RETN, /* ret (0xc3) */ XOP_MOV_RM8_IMM8, /* mov (0xc6 0) */ XOP_MOV_RM1632_IMM1632, /* mov ([0x66] 0xc7 0) */ XOP_LEAVE, /* leave (0xc9) */ - + XOP_RETF_IMM16, /* retn (0xca) */ + XOP_RETF, /* ret (0xcb) */ XOP_INT_3, /* int 3 (0xcc) */ XOP_INT, /* int (0xcd) */ + + XOP_ROL_RM8_1, /* rol (0xd0 0) */ + XOP_ROR_RM8_1, /* ror (0xd0 1) */ + XOP_RCL_RM8_1, /* rcl (0xd0 2) */ + XOP_RCR_RM8_1, /* rcr (0xd0 3) */ + XOP_SHL_RM8_1, /* shl (0xd0 4) */ + XOP_SHR_RM8_1, /* shr (0xd0 5) */ + XOP_SAL_RM8_1, /* sal (0xd0 6) */ + XOP_SAR_RM8_1, /* sar (0xd0 7) */ + XOP_ROL_RM1632_1, /* rol ([0x66] 0xd1 0) */ + XOP_ROR_RM1632_1, /* ror ([0x66] 0xd1 1) */ + XOP_RCL_RM1632_1, /* rcl ([0x66] 0xd1 2) */ + XOP_RCR_RM1632_1, /* rcr ([0x66] 0xd1 3) */ + XOP_SHL_RM1632_1, /* shl ([0x66] 0xd1 4) */ + XOP_SHR_RM1632_1, /* shr ([0x66] 0xd1 5) */ + XOP_SAL_RM1632_1, /* sal ([0x66] 0xd1 6) */ + XOP_SAR_RM1632_1, /* sar ([0x66] 0xd1 7) */ + XOP_ROL_RM8_CL, /* rol (0xd2 0) */ + XOP_ROR_RM8_CL, /* ror (0xd2 1) */ + XOP_RCL_RM8_CL, /* rcl (0xd2 2) */ + XOP_RCR_RM8_CL, /* rcr (0xd2 3) */ + XOP_SHL_RM8_CL, /* shl (0xd2 4) */ + XOP_SHR_RM8_CL, /* shr (0xd2 5) */ + XOP_SAL_RM8_CL, /* sal (0xd2 6) */ + XOP_SAR_RM8_CL, /* sar (0xd2 7) */ + XOP_ROL_RM1632_CL, /* rol ([0x66] 0xd3 0) */ + XOP_ROR_RM1632_CL, /* ror ([0x66] 0xd3 1) */ + XOP_RCL_RM1632_CL, /* rcl ([0x66] 0xd3 2) */ + XOP_RCR_RM1632_CL, /* rcr ([0x66] 0xd3 3) */ XOP_SHL_RM1632_CL, /* shl ([0x66] 0xd3 4) */ + XOP_SHR_RM1632_CL, /* shr ([0x66] 0xd3 5) */ + XOP_SAL_RM1632_CL, /* sal ([0x66] 0xd3 6) */ + XOP_SAR_RM1632_CL, /* sar ([0x66] 0xd3 7) */ + XOP_CALL_REL1632, /* call ([0x66] 0xe8) */ XOP_JMP_REL1632, /* jmp ([0x66] 0xe9) */ @@ -321,6 +362,8 @@ typedef enum _X86Opcodes XOP_MOVZX_R1632_RM8, /* movzx ([0x66] 0x0f 0xb6) */ + XOP_MOVZX_R1632_RM16, /* movzx ([0x66] 0x0f 0xb7) */ + XOP_MOVSX_R1632_RM8, /* movsx ([0x66] 0x0f 0xbe) */ XOP_MOVSX_R1632_RM1632, /* movsx ([0x66] 0x0f 0xbf) */ |