Supported nine extra x86 opcodes.

git-svn-id: svn://svn.gna.org/svn/chrysalide/trunk@66 abbe820e-26c8-41b2-8c08-b7b2b41f8b0a

1 files changed, 6 insertions, 0 deletions

diff --git a/src/arch/x86/opcodes.h b/src/arch/x86/opcodes.h
index f0bbc17..67858b0 100644
--- a/src/arch/x86/opcodes.h
+++ b/src/arch/x86/opcodes.h
@@ -192,6 +192,9 @@ GArchInstruction *x86_read_instr_mov_moffs8_al(const bin_t *, off_t *, off_t, vm
 /* Décode une instruction de type 'mov ..., [e]ax' (16/32 bits). */
 GArchInstruction *x86_read_instr_mov_moffs1632_e_ax(const bin_t *, off_t *, off_t, vmpa_t, X86Prefix, const GX86Processor *);
 
+/* Décode une instruction de type 'mov' (8 bits). */
+GArchInstruction *x86_read_instr_mov_r8_imm8(const bin_t *, off_t *, off_t, vmpa_t, X86Prefix, const GX86Processor *);
+
 /* Décode une instruction de type 'mov' (16 ou 32 bits). */
 GArchInstruction *x86_read_instr_mov_r1632_imm1632(const bin_t *, off_t *, off_t, vmpa_t, X86Prefix, const GX86Processor *);
 
@@ -273,6 +276,9 @@ GArchInstruction *x86_read_instr_sbb_rm1632_imm8(const bin_t *, off_t *, off_t,
 /* Décode une instruction de type 'sbb' (16 ou 32 bits). */
 GArchInstruction *x86_read_instr_sbb_rm1632_imm1632(const bin_t *, off_t *, off_t, vmpa_t, X86Prefix, const GX86Processor *);
 
+/* Décode une instruction de type 'scas al, ...' (8 bits). */
+GArchInstruction *x86_read_instr_scas_al_m8(const bin_t *, off_t *, off_t, vmpa_t, X86Prefix, const GX86Processor *);
+
 /* Décode une instruction de type 'shl' (16 ou 32 bits). */
 GArchInstruction *x86_read_instr_shl_rm1632_cl(const bin_t *, off_t *, off_t, vmpa_t, X86Prefix, const GX86Processor *);