diff options
Diffstat (limited to 'plugins/arm/v7/arm.c')
| -rw-r--r-- | plugins/arm/v7/arm.c | 1400 |
1 files changed, 1396 insertions, 4 deletions
diff --git a/plugins/arm/v7/arm.c b/plugins/arm/v7/arm.c index fac29a2..fc56f2d 100644 --- a/plugins/arm/v7/arm.c +++ b/plugins/arm/v7/arm.c @@ -31,7 +31,6 @@ #include <common/bconst.h> -#include "simd.h" #include "opcodes/arm_opcodes.h" #include "opcodes/opcodes_tmp_arm.h" @@ -103,6 +102,42 @@ static GArchInstruction *process_armv7_arm_unconditional_instructions(uint32_t); /* Désassemble une instruction ARMv7 liées au chapitre A5.7.1. */ static GArchInstruction *process_armv7_arm_memory_hints_advanced_simd_instructions_and_miscellaneous_instructions(uint32_t); +/* Désassemble une instruction ARMv7 liées au chapitre A7.4. */ +static GArchInstruction *process_armv7_arm_advanced_simd_data_processing_instructions(uint32_t); + +/* Désassemble une instruction ARMv7 liées au chapitre A7.4.1. */ +static GArchInstruction *process_armv7_arm_three_registers_of_the_same_length(uint32_t); + +/* Désassemble une instruction ARMv7 liées au chapitre A7.4.2. */ +static GArchInstruction *process_armv7_arm_three_registers_of_different_lengths(uint32_t); + +/* Désassemble une instruction ARMv7 liées au chapitre A7.4.3. */ +static GArchInstruction *process_armv7_arm_two_registers_and_a_scalar(uint32_t); + +/* Désassemble une instruction ARMv7 liées au chapitre A7.4.4. */ +static GArchInstruction *process_armv7_arm_two_registers_and_a_shift_amount(uint32_t); + +/* Désassemble une instruction ARMv7 liées au chapitre A7.4.5. */ +static GArchInstruction *process_armv7_arm_two_registers_miscellaneous(uint32_t); + +/* Désassemble une instruction ARMv7 liées au chapitre A7.4.6. */ +static GArchInstruction *process_armv7_arm_one_register_and_a_modified_immediate_value(uint32_t); + +/* Désassemble une instruction ARMv7 liées au chapitre A7.5. */ +static GArchInstruction *process_armv7_arm_floating_point_data_processing_instructions(uint32_t); + +/* Désassemble une instruction ARMv7 liées au chapitre A7.6. */ +static GArchInstruction *process_armv7_arm_extension_register_load_store_instructions(uint32_t); + +/* Désassemble une instruction ARMv7 liées au chapitre A7.7. */ +static GArchInstruction *process_armv7_arm_advanced_simd_element_or_structure_load_store_instructions(uint32_t); + +/* Désassemble une instruction ARMv7 liées au chapitre A7.8. */ +static GArchInstruction *process_armv7_arm_8_16_and_32_bit_transfer_between_arm_core_and_extension_registers(uint32_t); + +/* Désassemble une instruction ARMv7 liées au chapitre A7.9. */ +static GArchInstruction *process_armv7_arm_64_bit_transfers_between_arm_core_and_extension_registers(uint32_t); + /****************************************************************************** @@ -2064,7 +2099,21 @@ static GArchInstruction *process_armv7_arm_coprocessor_instructions_and_supervis else if ((coproc & b1110) == b1010) { - /* TODO */ + if ((op1 & b100000) == b000000 && (op1 & b111010) != b000000) + result = process_armv7_arm_extension_register_load_store_instructions(raw); + + else if ((op1 & b111110) == b000100) + result = process_armv7_arm_64_bit_transfers_between_arm_core_and_extension_registers(raw); + + else if ((op1 & b110000) == b100000) + { + if (op == b0) + result = process_armv7_arm_floating_point_data_processing_instructions(raw); + + else/* if (op == b1) */ + result = process_armv7_arm_8_16_and_32_bit_transfer_between_arm_core_and_extension_registers(raw); + + } } @@ -2191,10 +2240,10 @@ static GArchInstruction *process_armv7_arm_memory_hints_advanced_simd_instructio } else if ((op1 & b1100000) == b0100000) - result = process_armv7_simd_advanced_simd_data_processing_instructions(raw, true); + result = process_armv7_arm_advanced_simd_data_processing_instructions(raw); else if ((op1 & b1110001) == b1000000) - result = process_armv7_simd_advanced_simd_element_or_structure_load_store_instructions(raw, true); + result = process_armv7_arm_advanced_simd_element_or_structure_load_store_instructions(raw); else if ((op1 & b1110111) == b1000001) result = g_undef_instruction_new(IBS_NOP); @@ -2269,3 +2318,1346 @@ static GArchInstruction *process_armv7_arm_memory_hints_advanced_simd_instructio return result; } + + +/****************************************************************************** +* * +* Paramètres : raw = donnée brute de 16 bits à désassembler. * +* * +* Description : Désassemble une instruction ARMv7 liées au chapitre A7.4. * +* * +* Retour : Instruction mise en place ou NULL en cas d'échec. * +* * +* Remarques : - * +* * +******************************************************************************/ + +static GArchInstruction *process_armv7_arm_advanced_simd_data_processing_instructions(uint32_t raw) +{ + GArchInstruction *result; /* Instruction à renvoyer */ + uint32_t u; /* Champ 'u' à retrouver */ + uint32_t a; /* Champ 'a' à retrouver */ + uint32_t b; /* Champ 'b' à retrouver */ + uint32_t c; /* Champ 'c' à retrouver */ + + /** + * Suit les directives de : + * § A7.4 Advanced SIMD data-processing instructions + */ + + if ((raw & 0xfe000000) != 0xf2000000) return NULL; + + result = NULL; + + u = (raw >> 24) & b1; + a = (raw >> 19) & b11111; + b = (raw >> 8) & b1111; + c = (raw >> 4) & b1111; + + if ((a & b10000) == b00000) + result = process_armv7_arm_three_registers_of_the_same_length(raw); + + else if ((a & b10111) == b10000 && (c & b1001) == b0001) + result = process_armv7_arm_one_register_and_a_modified_immediate_value(raw); + + else if ((a & b10111) == b10001 && (c & b1001) == b0001) + result = process_armv7_arm_two_registers_and_a_shift_amount(raw); + + else if ((a & b10110) == b10010 && (c & b1001) == b0001) + result = process_armv7_arm_two_registers_and_a_shift_amount(raw); + + else if ((a & b10100) == b10100 && (c & b1001) == b0001) + result = process_armv7_arm_two_registers_and_a_shift_amount(raw); + + else if ((a & b10000) == b10000 && (c & b1001) == b1001) + result = process_armv7_arm_two_registers_and_a_shift_amount(raw); + + else if ((a & b10100) == b10000 && (c & b0101) == b0000) + result = process_armv7_arm_three_registers_of_different_lengths(raw); + + else if ((a & b10110) == b10100 && (c & b0101) == b0000) + result = process_armv7_arm_three_registers_of_different_lengths(raw); + + else if ((a & b10100) == b10000 && (c & b0101) == b0100) + result = process_armv7_arm_two_registers_and_a_scalar(raw); + + else if ((a & b10110) == b10100 && (c & b0101) == b0100) + result = process_armv7_arm_two_registers_and_a_scalar(raw); + + else if (u == b0 && (a & b10110) == b10110 && (c & b0001) == b0000) + result = armv7_read_arm_instr_a8_vext(raw); + + else if (u == b1 && (a & b10110) == b10110) + { + if ((b & b1000) == b0000 && (c & b0001) == b0000) + result = process_armv7_arm_two_registers_miscellaneous(raw); + + else if ((b & b1100) == b1000 && (c & b0001) == b0000) + result = armv7_read_arm_instr_a8_vtbl_vtbx(raw); + + else if (b == b1100 && (c & b1001) == b0000) + result = armv7_read_arm_instr_a8_vdup_scalar(raw); + + } + + return result; + +} + + +/****************************************************************************** +* * +* Paramètres : raw = donnée brute de 16 bits à désassembler. * +* * +* Description : Désassemble une instruction ARMv7 liées au chapitre A7.4.1. * +* * +* Retour : Instruction mise en place ou NULL en cas d'échec. * +* * +* Remarques : - * +* * +******************************************************************************/ + +static GArchInstruction *process_armv7_arm_three_registers_of_the_same_length(uint32_t raw) +{ + GArchInstruction *result; /* Instruction à renvoyer */ + uint32_t u; /* Champ 'u' à retrouver */ + uint32_t c; /* Champ 'c' à retrouver */ + uint32_t a; /* Champ 'a' à retrouver */ + uint32_t b; /* Champ 'b' à retrouver */ + + /** + * Suit les directives de : + * § A7.4.1 Three registers of the same length + */ + + if ((raw & 0xfe800000) != 0xf2000000) return NULL; + + result = NULL; + + u = (raw >> 24) & b1; + c = (raw >> 20) & b11; + a = (raw >> 8) & b1111; + b = (raw >> 4) & b1; + + if (a == b0000) + { + if (b == b0) + result = armv7_read_arm_instr_a8_vhadd_vhsub(raw); + + else/* if (b == b1)*/ + result = armv7_read_arm_instr_a8_vqadd(raw); + + } + + else if (a == b0001) + { + if (b == b0) + result = armv7_read_arm_instr_a8_vrhadd(raw); + + else/* if (b == b1)*/ + { + if (u == b0) + switch (c) + { + case b00: + result = armv7_read_arm_instr_a8_vand_register(raw); + break; + + case b01: + result = armv7_read_arm_instr_a8_vbic_register(raw); + break; + + case b10: + /* Cf. vmov_register aussi */ + result = armv7_read_arm_instr_a8_vorr_register(raw); + break; + + case b11: + result = armv7_read_arm_instr_a8_vorn_register(raw); + break; + + } + + else/* if (u == b1)*/ + switch (c) + { + case b00: + result = armv7_read_arm_instr_a8_veor(raw); + break; + + case b01: + result = armv7_read_arm_instr_a8_vbif_vbit_vbsl(raw); + break; + + case b10: + result = armv7_read_arm_instr_a8_vbif_vbit_vbsl(raw); + break; + + case b11: + result = armv7_read_arm_instr_a8_vbif_vbit_vbsl(raw); + break; + + } + + } + + } + + else if (a == b0010) + { + if (b == b0) + result = armv7_read_arm_instr_a8_vhadd_vhsub(raw); + + else/* if (b == b1)*/ + result = armv7_read_arm_instr_a8_vqsub(raw); + + } + + else if (a == b0011) + { + if (b == b0) + result = armv7_read_arm_instr_a8_vcgt_register(raw); + + else/* if (b == b1)*/ + result = armv7_read_arm_instr_a8_vcge_register(raw); + + } + + else if (a == b0100) + { + if (b == b0) + result = armv7_read_arm_instr_a8_vshl_register(raw); + + else/* if (b == b1)*/ + result = armv7_read_arm_instr_a8_vqshl_register(raw); + + } + + else if (a == b0101) + { + if (b == b0) + result = armv7_read_arm_instr_a8_vrshl(raw); + + else/* if (b == b1)*/ + result = armv7_read_arm_instr_a8_vqrshl(raw); + + } + + else if (a == b0110) + result = armv7_read_arm_instr_a8_vmax_vmin_integer(raw); + + else if (a == b0111) + { + if (b == b0) + result = armv7_read_arm_instr_a8_vabd_vabdl_integer(raw); + + else/* if (b == b1)*/ + result = armv7_read_arm_instr_a8_vaba_vabal(raw); + + } + + else if (a == b1000) + { + if (b == b0) + { + if (u == b0) + result = armv7_read_arm_instr_a8_vadd_integer(raw); + + else/* if (u == b1)*/ + result = armv7_read_arm_instr_a8_vsub_integer(raw); + + } + + else/* if (b == b1)*/ + { + if (u == b0) + result = armv7_read_arm_instr_a8_vtst(raw); + + else/* if (u == b1)*/ + result = armv7_read_arm_instr_a8_vceq_register(raw); + + } + + } + + else if (a == b1001) + { + if (b == b0) + result = armv7_read_arm_instr_a8_vmla_vmlal_vmls_vmlsl_integer(raw); + + else/* if (b == b1)*/ + result = armv7_read_arm_instr_a8_vmul_vmull_integer_and_polynomial(raw); + + } + + else if (a == b1010) + result = armv7_read_arm_instr_a8_vpmax_vpmin_integer(raw); + + else if (a == b1011) + { + if (b == b0) + { + if (u == b0) + result = armv7_read_arm_instr_a8_vqdmulh(raw); + + else/* if (u == b1)*/ + result = armv7_read_arm_instr_a8_vqrdmulh(raw); + + } + + else/* if (b == b1)*/ + { + if (u == b0) + result = armv7_read_arm_instr_a8_vpadd_integer(raw); + + } + + } + + else if (a == b1100) + { + if (b == b1 && u == b0) + result = armv7_read_arm_instr_a8_vfma_vfms(raw); + + } + + else if (a == b1101) + { + if (b == b0) + { + if (u == b0) + { + if ((c & b10) == b00) + result = armv7_read_arm_instr_a8_vadd_floating_point(raw); + + else/* if ((c & b10) == b10)*/ + result = armv7_read_arm_instr_a8_vsub_floating_point(raw); + + } + + else/* if (u == b1)*/ + { + if ((c & b10) == b00) + result = armv7_read_arm_instr_a8_vpadd_floating_point(raw); + + else/* if ((c & b10) == b10)*/ + result = armv7_read_arm_instr_a8_vabd_floating_point(raw); + + } + + } + + else/* if (b == b1)*/ + { + if (u == b0) + result = armv7_read_arm_instr_a8_vmla_vmls_floating_point(raw); + + else/* if (u == b1)*/ + { + if ((c & b10) == b00) + result = armv7_read_arm_instr_a8_vmul_floating_point(raw); + + } + + } + + } + + else if (a == b1110) + { + if (b == b0) + { + if (u == b0) + { + if ((c & b10) == b00) + result = armv7_read_arm_instr_a8_vceq_register(raw); + + } + + else/* if (u == b1)*/ + { + if ((c & b10) == b00) + result = armv7_read_arm_instr_a8_vcge_register(raw); + + else/* if ((c & b10) == b10)*/ + result = armv7_read_arm_instr_a8_vcgt_register(raw); + + } + + } + + else/* if (b == b1)*/ + { + if (u == b1) + result = armv7_read_arm_instr_a8_vacge_vacgt_vacle_vaclt(raw); + + } + + } + + else if (a == b1111) + { + if (b == b0) + { + if (u == b0) + result = armv7_read_arm_instr_a8_vmax_vmin_floating_point(raw); + + else/* if (u == b1)*/ + result = armv7_read_arm_instr_a8_vpmax_vpmin_floating_point(raw); + + } + + else/* if (b == b1)*/ + { + if (u == b0) + { + if ((c & b10) == b00) + result = armv7_read_arm_instr_a8_vrecps(raw); + + else/* if ((c & b10) == b10)*/ + result = armv7_read_arm_instr_a8_vrsqrts(raw); + + } + + } + + } + + return result; + +} + + +/****************************************************************************** +* * +* Paramètres : raw = donnée brute de 16 bits à désassembler. * +* * +* Description : Désassemble une instruction ARMv7 liées au chapitre A7.4.2. * +* * +* Retour : Instruction mise en place ou NULL en cas d'échec. * +* * +* Remarques : - * +* * +******************************************************************************/ + +static GArchInstruction *process_armv7_arm_three_registers_of_different_lengths(uint32_t raw) +{ + GArchInstruction *result; /* Instruction à renvoyer */ + uint32_t u; /* Champ 'u' à retrouver */ + uint32_t a; /* Champ 'a' à retrouver */ + + /** + * Suit les directives de : + * § A7.4.2 Three registers of different lengths + */ + + if ((raw & 0xfe800050) != 0xf2800000) return NULL; + + result = NULL; + + u = (raw >> 24) & b1; + a = (raw >> 8) & b1111; + + if ((a & b1110) == b0000) + result = armv7_read_arm_instr_a8_vaddl_vaddw(raw); + + else if ((a & b1110) == b0010) + result = armv7_read_arm_instr_a8_vsubl_vsubw(raw); + + else if (a == b0100) + { + if (u == b0) + result = armv7_read_arm_instr_a8_vaddhn(raw); + + else/* if (u == b1)*/ + result = armv7_read_arm_instr_a8_vraddhn(raw); + + } + + else if (a == b0101) + result = armv7_read_arm_instr_a8_vaba_vabal(raw); + + else if (a == b0110) + { + if (u == b0) + result = armv7_read_arm_instr_a8_vsubhn(raw); + + else/* if (u == b1)*/ + result = armv7_read_arm_instr_a8_vrsubhn(raw); + + } + + else if (a == b0111) + result = armv7_read_arm_instr_a8_vabd_vabdl_integer(raw); + + else if ((a & b1101) == b1000) + result = armv7_read_arm_instr_a8_vmla_vmlal_vmls_vmlsl_integer(raw); + + else if ((a & b1101) == b1001) + { + if (u == b0) + result = armv7_read_arm_instr_a8_vqdmlal_vqdmlsl(raw); + + } + + else if (a == b1100) + result = armv7_read_arm_instr_a8_vmul_vmull_integer_and_polynomial(raw); + + else if (a == b1101) + { + if (u == b0) + result = armv7_read_arm_instr_a8_vqdmull(raw); + + } + + else if (a == b1110) + result = armv7_read_arm_instr_a8_vmul_vmull_integer_and_polynomial(raw); + + return result; + +} + + +/****************************************************************************** +* * +* Paramètres : raw = donnée brute de 16 bits à désassembler. * +* * +* Description : Désassemble une instruction ARMv7 liées au chapitre A7.4.3. * +* * +* Retour : Instruction mise en place ou NULL en cas d'échec. * +* * +* Remarques : - * +* * +******************************************************************************/ + +static GArchInstruction *process_armv7_arm_two_registers_and_a_scalar(uint32_t raw) +{ + GArchInstruction *result; /* Instruction à renvoyer */ + uint32_t u; /* Champ 'u' à retrouver */ + uint32_t a; /* Champ 'a' à retrouver */ + + /** + * Suit les directives de : + * § A7.4.3 Two registers and a scalar + */ + + if ((raw & 0xfe800050) != 0xf2800040) return NULL; + + result = NULL; + + u = (raw >> 24) & b1; + a = (raw >> 8) & b1111; + + if ((a & b1010) == b0000) + result = armv7_read_arm_instr_a8_vmla_vmlal_vmls_vmlsl_by_scalar(raw); + + else if ((a & b1010) == b0010) + result = armv7_read_arm_instr_a8_vmla_vmlal_vmls_vmlsl_by_scalar(raw); + + else if ((a & b1011) == b0011 && u == b0) + result = armv7_read_arm_instr_a8_vqdmlal_vqdmlsl(raw); + + else if ((a & b1110) == b1000) + result = armv7_read_arm_instr_a8_vmul_vmull_by_scalar(raw); + + else if (a == b1010) + result = armv7_read_arm_instr_a8_vmul_vmull_by_scalar(raw); + + else if (a == b1011 && u == b0) + result = armv7_read_arm_instr_a8_vqdmull(raw); + + else if (a == b1100) + result = armv7_read_arm_instr_a8_vqdmulh(raw); + + else if (a == b1101) + result = armv7_read_arm_instr_a8_vqrdmulh(raw); + + return result; + +} + + +/****************************************************************************** +* * +* Paramètres : raw = donnée brute de 16 bits à désassembler. * +* * +* Description : Désassemble une instruction ARMv7 liées au chapitre A7.4.4. * +* * +* Retour : Instruction mise en place ou NULL en cas d'échec. * +* * +* Remarques : - * +* * +******************************************************************************/ + +static GArchInstruction *process_armv7_arm_two_registers_and_a_shift_amount(uint32_t raw) +{ + GArchInstruction *result; /* Instruction à renvoyer */ + uint32_t u; /* Champ 'u' à retrouver */ + uint32_t a; /* Champ 'a' à retrouver */ + uint32_t l; /* Champ 'l' à retrouver */ + uint32_t b; /* Champ 'b' à retrouver */ + + /** + * Suit les directives de : + * § A7.4.4 Two registers and a shift amount + */ + + if ((raw & 0xfe800010) != 0xf2800010) return NULL; + + result = NULL; + + u = (raw >> 24) & b1; + a = (raw >> 8) & b1111; + l = (raw >> 7) & b1; + b = (raw >> 6) & b1; + + if (a == b0000) + result = armv7_read_arm_instr_a8_vshr(raw); + + else if (a == b0001) + result = armv7_read_arm_instr_a8_vsra(raw); + + else if (a == b0010) + result = armv7_read_arm_instr_a8_vrshr(raw); + + else if (a == b0011) + result = armv7_read_arm_instr_a8_vrsra(raw); + + else if (a == b0100 && u == b1) + result = armv7_read_arm_instr_a8_vsri(raw); + + else if (a == b0101) + { + if (u == b0) + result = armv7_read_arm_instr_a8_vshl_immediate(raw); + + else/* if (u == b1)*/ + result = armv7_read_arm_instr_a8_vsli(raw); + + } + + else if ((a & b1110) == b0110) + result = armv7_read_arm_instr_a8_vqshl_vqshlu_immediate(raw); + + else if (a == b1000) + { + if (u == b0) + { + if (b == b0 && l == b0) + result = armv7_read_arm_instr_a8_vshrn(raw); + + else if (b == b1 && l == b0) + result = armv7_read_arm_instr_a8_vrshrn(raw); + + } + else/* if (u == b1)*/ + { + if (b == b0 && l == b0) + result = armv7_read_arm_instr_a8_vqshrn_vqshrun(raw); + + else if (b == b1 && l == b0) + result = armv7_read_arm_instr_a8_vqrshrn_vqrshrun(raw); + + } + + } + + else if (a == b1001) + { + if (b == b0 && l == b0) + result = armv7_read_arm_instr_a8_vqshrn_vqshrun(raw); + + else if (b == b1 && l == b0) + result = armv7_read_arm_instr_a8_vqrshrn_vqrshrun(raw); + + } + + else if (a == b1010 && b == b0 && l == b0) + { + result = armv7_read_arm_instr_a8_vshll(raw); + + /* ??? */ + if (result == NULL) + result = armv7_read_arm_instr_a8_vmovl(raw); + + } + + else if ((a & b1110) == b1110 && l == b0) + result = armv7_read_arm_instr_a8_vcvt_between_floating_point_and_fixed_point_advanced_simd(raw); + + return result; + +} + + +/****************************************************************************** +* * +* Paramètres : raw = donnée brute de 16 bits à désassembler. * +* * +* Description : Désassemble une instruction ARMv7 liées au chapitre A7.4.5. * +* * +* Retour : Instruction mise en place ou NULL en cas d'échec. * +* * +* Remarques : - * +* * +******************************************************************************/ + +static GArchInstruction *process_armv7_arm_two_registers_miscellaneous(uint32_t raw) +{ + GArchInstruction *result; /* Instruction à renvoyer */ + uint32_t a; /* Champ 'a' à retrouver */ + uint32_t b; /* Champ 'b' à retrouver */ + + /** + * Suit les directives de : + * § A7.4.5 Two registers, miscellaneous + */ + + if ((raw & 0xffb00810) != 0xf3b00000) return NULL; + + result = NULL; + + a = (raw >> 16) & b11; + b = (raw >> 6) & b11111; + + if (a == b00) + { + if ((b & b11110) == b00000) + result = armv7_read_arm_instr_a8_vrev16_vrev32_vrev64(raw); + + else if ((b & b11110) == b00010) + result = armv7_read_arm_instr_a8_vrev16_vrev32_vrev64(raw); + + else if ((b & b11110) == b00100) + result = armv7_read_arm_instr_a8_vrev16_vrev32_vrev64(raw); + + else if ((b & b11100) == b01000) + result = armv7_read_arm_instr_a8_vpaddl(raw); + + else if ((b & b11110) == b10000) + result = armv7_read_arm_instr_a8_vcls(raw); + + else if ((b & b11110) == b10010) + result = armv7_read_arm_instr_a8_vclz(raw); + + else if ((b & b11110) == b10100) + result = armv7_read_arm_instr_a8_vcnt(raw); + + else if ((b & b11110) == b10110) + result = armv7_read_arm_instr_a8_vmvn_register(raw); + + else if ((b & b11100) == b11000) + result = armv7_read_arm_instr_a8_vpadal(raw); + + else if ((b & b11110) == b11100) + result = armv7_read_arm_instr_a8_vqabs(raw); + + else if ((b & b11110) == b11110) + result = armv7_read_arm_instr_a8_vqneg(raw); + + } + + else if (a == b01) + { + if ((b & b01110) == b00000) + result = armv7_read_arm_instr_a8_vcgt_immediate_0(raw); + + else if ((b & b01110) == b00010) + result = armv7_read_arm_instr_a8_vcge_immediate_0(raw); + + else if ((b & b01110) == b00100) + result = armv7_read_arm_instr_a8_vceq_immediate_0(raw); + + else if ((b & b01110) == b00110) + result = armv7_read_arm_instr_a8_vcle_immediate_0(raw); + + else if ((b & b01110) == b01000) + result = armv7_read_arm_instr_a8_vclt_immediate_0(raw); + + else if ((b & b01110) == b01100) + result = armv7_read_arm_instr_a8_vabs(raw); + + else if ((b & b01110) == b01110) + result = armv7_read_arm_instr_a8_vneg(raw); + + } + + return result; + +} + + +/****************************************************************************** +* * +* Paramètres : raw = donnée brute de 16 bits à désassembler. * +* * +* Description : Désassemble une instruction ARMv7 liées au chapitre A7.4.6. * +* * +* Retour : Instruction mise en place ou NULL en cas d'échec. * +* * +* Remarques : - * +* * +******************************************************************************/ + +static GArchInstruction *process_armv7_arm_one_register_and_a_modified_immediate_value(uint32_t raw) +{ + GArchInstruction *result; /* Instruction à renvoyer */ + uint32_t cmode; /* Champ 'cmode' à retrouver */ + uint32_t op; /* Champ 'op' à retrouver */ + + /** + * Suit les directives de : + * § A7.4.6 One register and a modified immediate value + */ + + if ((raw & 0xfeb80090) != 0xf2800010) return NULL; + + result = NULL; + + cmode = (raw >> 8) & b1111; + op = (raw >> 5) & b1; + + if (op == b0) + { + if ((cmode & b1001) == b0000) + result = armv7_read_arm_instr_a8_vmov_immediate(raw); + + else if ((cmode & b1001) == b0001) + result = armv7_read_arm_instr_a8_vorr_immediate(raw); + + else if ((cmode & b1101) == b1000) + result = armv7_read_arm_instr_a8_vmov_immediate(raw); + + else if ((cmode & b1101) == b1001) + result = armv7_read_arm_instr_a8_vorr_immediate(raw); + + else if ((cmode & b1100) == b1100) + result = armv7_read_arm_instr_a8_vmov_immediate(raw); + + } + + else/* if (op == b1)*/ + { + if ((cmode & b1001) == b0000) + result = armv7_read_arm_instr_a8_vmvn_immediate(raw); + + else if ((cmode & b1001) == b0001) + result = armv7_read_arm_instr_a8_vbic_immediate(raw); + + else if ((cmode & b1101) == b1000) + result = armv7_read_arm_instr_a8_vmvn_immediate(raw); + + else if ((cmode & b1101) == b1001) + result = armv7_read_arm_instr_a8_vbic_immediate(raw); + + else if ((cmode & b1110) == b1100) + result = armv7_read_arm_instr_a8_vmvn_immediate(raw); + + else if (cmode == b1110) + result = armv7_read_arm_instr_a8_vmov_immediate(raw); + + else if (cmode == b1111) + result = g_undef_instruction_new(IBS_UNDEFINED); + + } + + return result; + +} + + +/****************************************************************************** +* * +* Paramètres : raw = donnée brute de 16 bits à désassembler. * +* * +* Description : Désassemble une instruction ARMv7 liées au chapitre A7.5. * +* * +* Retour : Instruction mise en place ou NULL en cas d'échec. * +* * +* Remarques : - * +* * +******************************************************************************/ + +static GArchInstruction *process_armv7_arm_floating_point_data_processing_instructions(uint32_t raw) +{ + GArchInstruction *result; /* Instruction à renvoyer */ + uint32_t opc1; /* Champ 'opc1' à retrouver */ + uint32_t opc2; /* Champ 'opc2' à retrouver */ + uint32_t opc3; /* Champ 'opc3' à retrouver */ + + /** + * Suit les directives de : + * § A7.5 Floating-point data-processing instructions + */ + + if ((raw & 0x0f000e10) != 0xee000a00) return NULL; + + result = NULL; + + opc1 = (raw >> 20) & b1111; + opc2 = (raw >> 16) & b1111; + opc3 = (raw >> 6) & b11; + + + if ((opc1 & b1011) == b0000) + result = armv7_read_arm_instr_a8_vmla_vmls_floating_point(raw); + + else if ((opc1 & b1011) == b0001) + result = armv7_read_arm_instr_a8_vnmla_vnmls_vnmul(raw); + + else if ((opc1 & b1011) == b0010) + { + if ((opc3 & b01) == b01) + result = armv7_read_arm_instr_a8_vnmla_vnmls_vnmul(raw); + + else/* if ((opc3 & b01) == b00)*/ + result = armv7_read_arm_instr_a8_vmul_floating_point(raw); + + } + + else if ((opc1 & b1011) == b0011) + { + if ((opc3 & b01) == b00) + result = armv7_read_arm_instr_a8_vadd_floating_point(raw); + + else/* if ((opc3 & b01) == b01)*/ + result = armv7_read_arm_instr_a8_vsub_floating_point(raw); + + } + + else if ((opc1 & b1011) == b1000) + { + if ((opc3 & b01) == b00) + result = armv7_read_arm_instr_a8_vdiv(raw); + + } + + else if ((opc1 & b1011) == b1001) + result = armv7_read_arm_instr_a8_vfnma_vfnms(raw); + + else if ((opc1 & b1011) == b1010) + result = armv7_read_arm_instr_a8_vfma_vfms(raw); + + else if ((opc1 & b1011) == b1011) + { + if ((opc3 & b01) == b00) + result = armv7_read_arm_instr_a8_vmov_immediate(raw); + + else if (opc2 == b0000) + { + if (opc3 == b01) + result = armv7_read_arm_instr_a8_vmov_register(raw); + + else if (opc3 == b11) + result = armv7_read_arm_instr_a8_vabs(raw); + + } + + else if (opc2 == b0001) + { + if (opc3 == b01) + result = armv7_read_arm_instr_a8_vneg(raw); + + else if (opc3 == b11) + result = armv7_read_arm_instr_a8_vsqrt(raw); + + } + + else if ((opc2 & b1110) == b0010 && (opc3 & b01) == b01) + result = armv7_read_arm_instr_a8_vcvtb_vcvtt(raw); + + else if ((opc2 & b1110) == b0100 && (opc3 & b01) == b01) + result = armv7_read_arm_instr_a8_vcmp_vcmpe(raw); + + else if (opc2 == b0111 && opc3 == b11) + result = armv7_read_arm_instr_a8_vcvt_between_double_precision_and_single_precision(raw); + + else if (opc2 == b1000 && (opc3 & b01) == b01) + result = armv7_read_arm_instr_a8_vcvt_vcvtr_between_floating_point_and_integer_floating_point(raw); + + else if ((opc2 & b1110) == b1010 && (opc3 & b01) == b01) + result = armv7_read_arm_instr_a8_vcvt_between_floating_point_and_fixed_point_floating_point(raw); + + else if ((opc2 & b1110) == b1100 && (opc3 & b01) == b01) + result = armv7_read_arm_instr_a8_vcvt_vcvtr_between_floating_point_and_integer_floating_point(raw); + + else if ((opc2 & b1110) == b1110 && (opc3 & b01) == b01) + result = armv7_read_arm_instr_a8_vcvt_between_floating_point_and_fixed_point_floating_point(raw); + + } + + return result; + +} + + +/****************************************************************************** +* * +* Paramètres : raw = donnée brute de 16 bits à désassembler. * +* * +* Description : Désassemble une instruction ARMv7 liées au chapitre A7.6. * +* * +* Retour : Instruction mise en place ou NULL en cas d'échec. * +* * +* Remarques : - * +* * +******************************************************************************/ + +static GArchInstruction *process_armv7_arm_extension_register_load_store_instructions(uint32_t raw) +{ + GArchInstruction *result; /* Instruction à renvoyer */ + uint32_t opcode; /* Champ 'opcode' à retrouver */ + uint32_t rn; /* Champ 'rn' à retrouver */ + + /** + * Suit les directives de : + * § A7.6 Extension register load/store instructions + */ + + if ((raw & 0x0e000e00) != 0x0c000a00) return NULL; + + result = NULL; + + opcode = (raw >> 20) & b11111; + rn = (raw >> 16) & b1111; + + if ((opcode & b11110) == b00100) + result = process_armv7_arm_64_bit_transfers_between_arm_core_and_extension_registers(raw); + + else if ((opcode & b11011) == b01000) + result = armv7_read_arm_instr_a8_vstm(raw); + + else if ((opcode & b11011) == b01010) + result = armv7_read_arm_instr_a8_vstm(raw); + + else if ((opcode & b10011) == b10000) + result = armv7_read_arm_instr_a8_vstr(raw); + + else if ((opcode & b11011) == b10010) + { + if (rn != b1101) + result = armv7_read_arm_instr_a8_vstm(raw); + + else/* if (rn == b1101)*/ + result = armv7_read_arm_instr_a8_vpush(raw); + + } + + else if ((opcode & b11011) == b01001) + result = armv7_read_arm_instr_a8_vldm(raw); + + else if ((opcode & b11011) == b01011) + { + if (rn != 1101) + result = armv7_read_arm_instr_a8_vldm(raw); + + else/* if (rn == 1101)*/ + result = armv7_read_arm_instr_a8_vpop(raw); + + } + + else if ((opcode & b10011) == b10001) + result = armv7_read_arm_instr_a8_vldr(raw); + + else if ((opcode & b11011) == b10011) + result = armv7_read_arm_instr_a8_vldm(raw); + + return result; + +} + + +/****************************************************************************** +* * +* Paramètres : raw = donnée brute de 16 bits à désassembler. * +* * +* Description : Désassemble une instruction ARMv7 liées au chapitre A7.7. * +* * +* Retour : Instruction mise en place ou NULL en cas d'échec. * +* * +* Remarques : - * +* * +******************************************************************************/ + +static GArchInstruction *process_armv7_arm_advanced_simd_element_or_structure_load_store_instructions(uint32_t raw) +{ + GArchInstruction *result; /* Instruction à renvoyer */ + uint32_t a; /* Champ 'a' à retrouver */ + uint32_t l; /* Champ 'l' à retrouver */ + uint32_t b; /* Champ 'b' à retrouver */ + + /** + * Suit les directives de : + * § A7.7 Advanced SIMD element or structure load/store instructions + */ + + if ((raw & 0xff100000) != 0xf4000000) return NULL; + + result = NULL; + + a = (raw >> 23) & b1; + l = (raw >> 21) & b1; + b = (raw >> 8) & b1111; + + if (l == b0) + { + if (a == b0) + { + if (b == b0010) + result = armv7_read_arm_instr_a8_vst1_multiple_single_elements(raw); + + else if ((b & b1110) == b0110) + result = armv7_read_arm_instr_a8_vst1_multiple_single_elements(raw); + + else if (b == b1010) + result = armv7_read_arm_instr_a8_vst1_multiple_single_elements(raw); + + else if (b == b0011) + result = armv7_read_arm_instr_a8_vst2_multiple_2_element_structures(raw); + + else if ((b & b1110) == b1000) + result = armv7_read_arm_instr_a8_vst2_multiple_2_element_structures(raw); + + else if ((b & b1110) == b0100) + result = armv7_read_arm_instr_a8_vst3_multiple_3_element_structures(raw); + + else if ((b & b1110) == b0000) + result = armv7_read_arm_instr_a8_vst4_multiple_4_element_structures(raw); + + } + + else/* if (a == b1)*/ + { + if ((b & b1011) == b0000) + result = armv7_read_arm_instr_a8_vst1_single_element_from_one_lane(raw); + + else if (b == b1000) + result = armv7_read_arm_instr_a8_vst1_single_element_from_one_lane(raw); + + else if ((b & b1011) == b0001) + result = armv7_read_arm_instr_a8_vst2_single_2_element_structure_from_one_lane(raw); + + else if (b == b1001) + result = armv7_read_arm_instr_a8_vst2_single_2_element_structure_from_one_lane(raw); + + else if ((b & b1011) == b0010) + result = armv7_read_arm_instr_a8_vst3_single_3_element_structure_from_one_lane(raw); + + else if (b == b1010) + result = armv7_read_arm_instr_a8_vst3_single_3_element_structure_from_one_lane(raw); + + else if ((b & b1011) == b0011) + result = armv7_read_arm_instr_a8_vst4_single_4_element_structure_from_one_lane(raw); + + else if (b == b1011) + result = armv7_read_arm_instr_a8_vst4_single_4_element_structure_from_one_lane(raw); + + } + + } + + else/* if (l == b1)*/ + { + if (a == b0) + { + if (b == b0010) + result = armv7_read_arm_instr_a8_vld1_multiple_single_elements(raw); + + else if ((b & b1110) == b0110) + result = armv7_read_arm_instr_a8_vld1_multiple_single_elements(raw); + + else if (b == b1010) + result = armv7_read_arm_instr_a8_vld1_multiple_single_elements(raw); + + else if (b == b0011) + result = armv7_read_arm_instr_a8_vld2_multiple_2_element_structures(raw); + + else if ((b & b1110) == b1000) + result = armv7_read_arm_instr_a8_vld2_multiple_2_element_structures(raw); + + else if ((b & b1110) == b0100) + result = armv7_read_arm_instr_a8_vld3_multiple_3_element_structures(raw); + + else if ((b & b1110) == b0000) + result = armv7_read_arm_instr_a8_vld4_multiple_4_element_structures(raw); + + } + + else/* if (a == b1)*/ + { + if ((b & b1011) == b0000) + result = armv7_read_arm_instr_a8_vld1_single_element_to_one_lane(raw); + + else if (b == b1000) + result = armv7_read_arm_instr_a8_vld1_single_element_to_one_lane(raw); + + else if (b == b1100) + result = armv7_read_arm_instr_a8_vld1_single_element_to_all_lanes(raw); + + else if ((b & b1011) == b0001) + result = armv7_read_arm_instr_a8_vld2_single_2_element_structure_to_one_lane(raw); + + else if (b == b1001) + result = armv7_read_arm_instr_a8_vld2_single_2_element_structure_to_one_lane(raw); + + else if (b == b1101) + result = armv7_read_arm_instr_a8_vld2_single_2_element_structure_to_all_lanes(raw); + + else if ((b & b1011) == b0010) + result = armv7_read_arm_instr_a8_vld3_single_3_element_structure_to_one_lane(raw); + + else if (b == b1010) + result = armv7_read_arm_instr_a8_vld3_single_3_element_structure_to_one_lane(raw); + + else if (b == b1110) + result = armv7_read_arm_instr_a8_vld3_single_3_element_structure_to_all_lanes(raw); + + else if ((b & b1011) == b0011) + result = armv7_read_arm_instr_a8_vld4_single_4_element_structure_to_one_lane(raw); + + else if (b == b1011) + result = armv7_read_arm_instr_a8_vld4_single_4_element_structure_to_one_lane(raw); + + else if (b == b1111) + result = armv7_read_arm_instr_a8_vld4_single_4_element_structure_to_all_lanes(raw); + + } + + } + + return result; + +} + + +/****************************************************************************** +* * +* Paramètres : raw = donnée brute de 16 bits à désassembler. * +* * +* Description : Désassemble une instruction ARMv7 liées au chapitre A7.8. * +* * +* Retour : Instruction mise en place ou NULL en cas d'échec. * +* * +* Remarques : - * +* * +******************************************************************************/ + +static GArchInstruction *process_armv7_arm_8_16_and_32_bit_transfer_between_arm_core_and_extension_registers(uint32_t raw) +{ + GArchInstruction *result; /* Instruction à renvoyer */ + uint32_t a; /* Champ 'a' à retrouver */ + uint32_t l; /* Champ 'l' à retrouver */ + uint32_t c; /* Champ 'c' à retrouver */ + uint32_t b; /* Champ 'b' à retrouver */ + + /** + * Suit les directives de : + * § A7.8 8, 16, and 32-bit transfer between ARM core and extension registers + */ + + if ((raw & 0x0f000e10) != 0x0e000a10) return NULL; + + result = NULL; + + a = (raw >> 21) & b111; + l = (raw >> 20) & b1; + c = (raw >> 8) & b1; + b = (raw >> 5) & b11; + + if (l == b0) + { + if (c == b0) + { + if (a == b000) + result = armv7_read_arm_instr_a8_vmov_between_arm_core_register_and_single_precision_register(raw); + + else if (a == b111) + { + result = armv7_read_arm_instr_a8_vmsr(raw); /* B9 ? */ + + if (result == NULL /* ! */) + result = armv7_read_arm_instr_b9_vmsr(raw); + + } + + } + + else/* if (c == b1)*/ + { + if ((a & b100) == b000) + result = armv7_read_arm_instr_a8_vmov_arm_core_register_to_scalar(raw); + + else if (/*(a & b100) == b000) && */(b & b10) == b00) + result = armv7_read_arm_instr_a8_vdup_arm_core_register(raw); + + } + + } + + else/* if (l == b1)*/ + { + if (c == b0) + { + if (a == b000) + result = armv7_read_arm_instr_a8_vmov_between_arm_core_register_and_single_precision_register(raw); + + else if (a == b111) + { + result = armv7_read_arm_instr_a8_vmrs(raw); /* B9 ? */ + + if (result == NULL /* ! */) + result = armv7_read_arm_instr_b9_vmrs(raw); + + } + + } + + else/* if (c == b1)*/ + result = armv7_read_arm_instr_a8_vmov_scalar_to_arm_core_register(raw); + + } + + return result; + +} + + +/****************************************************************************** +* * +* Paramètres : raw = donnée brute de 16 bits à désassembler. * +* * +* Description : Désassemble une instruction ARMv7 liées au chapitre A7.9. * +* * +* Retour : Instruction mise en place ou NULL en cas d'échec. * +* * +* Remarques : - * +* * +******************************************************************************/ + +static GArchInstruction *process_armv7_arm_64_bit_transfers_between_arm_core_and_extension_registers(uint32_t raw) +{ + GArchInstruction *result; /* Instruction à renvoyer */ + uint32_t c; /* Champ 'c' à retrouver */ + uint32_t op; /* Champ 'op' à retrouver */ + + /** + * Suit les directives de : + * § A7.9 64-bit transfers between ARM core and extension registers + */ + + if ((raw & 0x0fe00e00) != 0x0c400a00) return NULL; + + result = NULL; + + c = (raw >> 8) & b1; + op = (raw >> 4) & b1111; + + if (c == b0 && (op & b1101) == 0001) + result = armv7_read_arm_instr_a8_vmov_between_two_arm_core_registers_and_two_single_precision_registers(raw); + + else if (c == b1 && (op & b1101) == 0001) + result = armv7_read_arm_instr_a8_vmov_between_two_arm_core_registers_and_a_doubleword_extension_register(raw); + + return result; + +} |