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Diffstat (limited to 'plugins/arm/v7/opdefs/A88283_vadd.d')
| -rw-r--r-- | plugins/arm/v7/opdefs/A88283_vadd.d | 237 |
1 files changed, 237 insertions, 0 deletions
diff --git a/plugins/arm/v7/opdefs/A88283_vadd.d b/plugins/arm/v7/opdefs/A88283_vadd.d new file mode 100644 index 0000000..096dbc0 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88283_vadd.d @@ -0,0 +1,237 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title VADD (floating-point) + +@id 275 + +@desc { + + Vector Add adds corresponding elements in two vectors, and places the results in the destination vector. Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the security state and mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. Summary of general controls of CP10 and CP11 functionality on page B1-1230 and Summary of access controls for Advanced SIMD functionality on page B1-1232 summarize these controls. ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available as a VFP instruction encoding, see Conditional execution on page A8-288. + +} + +@encoding (T1) { + + @word 1 1 1 0 1 1 1 1 0 D(1) 0 sz(1) Vn(4) Vd(4) 1 1 0 1 N(1) Q(1) M(1) 0 Vm(4) + + @syntax { + + @subid 903 + + @assert { + + Q == 1 + sz == 0 + + } + + @conv { + + qwvec_D = QuadWordVector(D:Vd) + qwvec_N = QuadWordVector(N:Vn) + qwvec_M = QuadWordVector(M:Vm) + + } + + @asm vadd.f32 ?qwvec_D qwvec_N qwvec_M + + } + + @syntax { + + @subid 904 + + @assert { + + Q == 0 + sz == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_N = DoubleWordVector(N:Vn) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vadd.f32 ?dwvec_D dwvec_N dwvec_M + + } + +} + +@encoding (T2) { + + @word 1 1 1 0 1 1 1 0 0 D(1) 1 1 Vn(4) Vd(4) 1 0 1 sz(1) N(1) 0 M(1) 0 Vm(4) + + @syntax { + + @subid 905 + + @assert { + + sz == 0 + + } + + @conv { + + swvec_D = SingleWordVector(Vd:D) + swvec_N = SingleWordVector(Vn:N) + swvec_M = SingleWordVector(Vm:M) + + } + + @asm vadd.f32 ?swvec_D swvec_N swvec_M + + } + + @syntax { + + @subid 906 + + @assert { + + sz == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_N = DoubleWordVector(N:Vn) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vadd.f64 ?dwvec_D dwvec_N dwvec_M + + } + +} + +@encoding (A1) { + + @word 1 1 1 0 1 1 1 1 0 D(1) 0 sz(1) Vn(4) Vd(4) 1 1 0 1 N(1) Q(1) M(1) 0 Vm(4) + + @syntax { + + @subid 907 + + @assert { + + Q == 1 + sz == 0 + + } + + @conv { + + qwvec_D = QuadWordVector(D:Vd) + qwvec_N = QuadWordVector(N:Vn) + qwvec_M = QuadWordVector(M:Vm) + + } + + @asm vadd.f32 ?qwvec_D qwvec_N qwvec_M + + } + + @syntax { + + @subid 908 + + @assert { + + Q == 0 + sz == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_N = DoubleWordVector(N:Vn) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vadd.f32 ?dwvec_D dwvec_N dwvec_M + + } + +} + +@encoding (A2) { + + @word 1 1 1 0 1 1 1 0 0 D(1) 1 1 Vn(4) Vd(4) 1 0 1 sz(1) N(1) 0 M(1) 0 Vm(4) + + @syntax { + + @subid 909 + + @assert { + + sz == 0 + + } + + @conv { + + swvec_D = SingleWordVector(Vd:D) + swvec_N = SingleWordVector(Vn:N) + swvec_M = SingleWordVector(Vm:M) + + } + + @asm vadd.f32 ?swvec_D swvec_N swvec_M + + } + + @syntax { + + @subid 910 + + @assert { + + sz == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_N = DoubleWordVector(N:Vn) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vadd.f64 ?dwvec_D dwvec_N dwvec_M + + } + +} + |