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Diffstat (limited to 'plugins/arm/v7/opdefs/A88319_vh.d')
| -rw-r--r-- | plugins/arm/v7/opdefs/A88319_vh.d | 1245 |
1 files changed, 1245 insertions, 0 deletions
diff --git a/plugins/arm/v7/opdefs/A88319_vh.d b/plugins/arm/v7/opdefs/A88319_vh.d new file mode 100644 index 0000000..efb94bc --- /dev/null +++ b/plugins/arm/v7/opdefs/A88319_vh.d @@ -0,0 +1,1245 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title VHADD, VHSUB + +@id 303 + +@desc { + + Vector Halving Add adds corresponding elements in two vectors of integers, shifts each result right one bit, and places the final results in the destination vector. The results of the halving operations are truncated (for rounded results see VRHADD on page A8-1030). Vector Halving Subtract subtracts the elements of the second operand from the corresponding elements of the first operand, shifts each result right one bit, and places the final results in the destination vector. The results of the halving operations are truncated (there is no rounding version). The operand and result elements are all the same type, and can be any one of: • 8-bit, 16-bit, or 32-bit signed integers • 8-bit, 16-bit, or 32-bit unsigned integers. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. Summary of access controls for Advanced SIMD functionality on page B1-1232 summarizes these controls. ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available as a VFP instruction encoding, see Conditional execution on page A8-288. + +} + +@encoding (T1) { + + @word 1 1 1 U(1) 1 1 1 1 0 D(1) size(2) Vn(4) Vd(4) 0 0 op(1) 0 N(1) Q(1) M(1) 0 Vm(4) + + @syntax { + + @subid 1273 + + @assert { + + Q == 1 + op == 0 + size == 0 + U == 0 + + } + + @conv { + + qwvec_D = QuadWordVector(D:Vd) + qwvec_N = QuadWordVector(N:Vn) + qwvec_M = QuadWordVector(M:Vm) + + } + + @asm vhadd.s8 ?qwvec_D qwvec_N qwvec_M + + } + + @syntax { + + @subid 1274 + + @assert { + + Q == 1 + op == 0 + size == 1 + U == 0 + + } + + @conv { + + qwvec_D = QuadWordVector(D:Vd) + qwvec_N = QuadWordVector(N:Vn) + qwvec_M = QuadWordVector(M:Vm) + + } + + @asm vhadd.s16 ?qwvec_D qwvec_N qwvec_M + + } + + @syntax { + + @subid 1275 + + @assert { + + Q == 1 + op == 0 + size == 10 + U == 0 + + } + + @conv { + + qwvec_D = QuadWordVector(D:Vd) + qwvec_N = QuadWordVector(N:Vn) + qwvec_M = QuadWordVector(M:Vm) + + } + + @asm vhadd.s32 ?qwvec_D qwvec_N qwvec_M + + } + + @syntax { + + @subid 1276 + + @assert { + + Q == 1 + op == 0 + size == 0 + U == 1 + + } + + @conv { + + qwvec_D = QuadWordVector(D:Vd) + qwvec_N = QuadWordVector(N:Vn) + qwvec_M = QuadWordVector(M:Vm) + + } + + @asm vhadd.u8 ?qwvec_D qwvec_N qwvec_M + + } + + @syntax { + + @subid 1277 + + @assert { + + Q == 1 + op == 0 + size == 1 + U == 1 + + } + + @conv { + + qwvec_D = QuadWordVector(D:Vd) + qwvec_N = QuadWordVector(N:Vn) + qwvec_M = QuadWordVector(M:Vm) + + } + + @asm vhadd.u16 ?qwvec_D qwvec_N qwvec_M + + } + + @syntax { + + @subid 1278 + + @assert { + + Q == 1 + op == 0 + size == 10 + U == 1 + + } + + @conv { + + qwvec_D = QuadWordVector(D:Vd) + qwvec_N = QuadWordVector(N:Vn) + qwvec_M = QuadWordVector(M:Vm) + + } + + @asm vhadd.u32 ?qwvec_D qwvec_N qwvec_M + + } + + @syntax { + + @subid 1279 + + @assert { + + Q == 1 + op == 1 + size == 0 + U == 0 + + } + + @conv { + + qwvec_D = QuadWordVector(D:Vd) + qwvec_N = QuadWordVector(N:Vn) + qwvec_M = QuadWordVector(M:Vm) + + } + + @asm vhsub.s8 ?qwvec_D qwvec_N qwvec_M + + } + + @syntax { + + @subid 1280 + + @assert { + + Q == 1 + op == 1 + size == 1 + U == 0 + + } + + @conv { + + qwvec_D = QuadWordVector(D:Vd) + qwvec_N = QuadWordVector(N:Vn) + qwvec_M = QuadWordVector(M:Vm) + + } + + @asm vhsub.s16 ?qwvec_D qwvec_N qwvec_M + + } + + @syntax { + + @subid 1281 + + @assert { + + Q == 1 + op == 1 + size == 10 + U == 0 + + } + + @conv { + + qwvec_D = QuadWordVector(D:Vd) + qwvec_N = QuadWordVector(N:Vn) + qwvec_M = QuadWordVector(M:Vm) + + } + + @asm vhsub.s32 ?qwvec_D qwvec_N qwvec_M + + } + + @syntax { + + @subid 1282 + + @assert { + + Q == 1 + op == 1 + size == 0 + U == 1 + + } + + @conv { + + qwvec_D = QuadWordVector(D:Vd) + qwvec_N = QuadWordVector(N:Vn) + qwvec_M = QuadWordVector(M:Vm) + + } + + @asm vhsub.u8 ?qwvec_D qwvec_N qwvec_M + + } + + @syntax { + + @subid 1283 + + @assert { + + Q == 1 + op == 1 + size == 1 + U == 1 + + } + + @conv { + + qwvec_D = QuadWordVector(D:Vd) + qwvec_N = QuadWordVector(N:Vn) + qwvec_M = QuadWordVector(M:Vm) + + } + + @asm vhsub.u16 ?qwvec_D qwvec_N qwvec_M + + } + + @syntax { + + @subid 1284 + + @assert { + + Q == 1 + op == 1 + size == 10 + U == 1 + + } + + @conv { + + qwvec_D = QuadWordVector(D:Vd) + qwvec_N = QuadWordVector(N:Vn) + qwvec_M = QuadWordVector(M:Vm) + + } + + @asm vhsub.u32 ?qwvec_D qwvec_N qwvec_M + + } + + @syntax { + + @subid 1285 + + @assert { + + Q == 0 + op == 0 + size == 0 + U == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_N = DoubleWordVector(N:Vn) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vhadd.s8 ?dwvec_D dwvec_N dwvec_M + + } + + @syntax { + + @subid 1286 + + @assert { + + Q == 0 + op == 0 + size == 1 + U == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_N = DoubleWordVector(N:Vn) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vhadd.s16 ?dwvec_D dwvec_N dwvec_M + + } + + @syntax { + + @subid 1287 + + @assert { + + Q == 0 + op == 0 + size == 10 + U == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_N = DoubleWordVector(N:Vn) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vhadd.s32 ?dwvec_D dwvec_N dwvec_M + + } + + @syntax { + + @subid 1288 + + @assert { + + Q == 0 + op == 0 + size == 0 + U == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_N = DoubleWordVector(N:Vn) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vhadd.u8 ?dwvec_D dwvec_N dwvec_M + + } + + @syntax { + + @subid 1289 + + @assert { + + Q == 0 + op == 0 + size == 1 + U == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_N = DoubleWordVector(N:Vn) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vhadd.u16 ?dwvec_D dwvec_N dwvec_M + + } + + @syntax { + + @subid 1290 + + @assert { + + Q == 0 + op == 0 + size == 10 + U == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_N = DoubleWordVector(N:Vn) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vhadd.u32 ?dwvec_D dwvec_N dwvec_M + + } + + @syntax { + + @subid 1291 + + @assert { + + Q == 0 + op == 1 + size == 0 + U == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_N = DoubleWordVector(N:Vn) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vhsub.s8 ?dwvec_D dwvec_N dwvec_M + + } + + @syntax { + + @subid 1292 + + @assert { + + Q == 0 + op == 1 + size == 1 + U == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_N = DoubleWordVector(N:Vn) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vhsub.s16 ?dwvec_D dwvec_N dwvec_M + + } + + @syntax { + + @subid 1293 + + @assert { + + Q == 0 + op == 1 + size == 10 + U == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_N = DoubleWordVector(N:Vn) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vhsub.s32 ?dwvec_D dwvec_N dwvec_M + + } + + @syntax { + + @subid 1294 + + @assert { + + Q == 0 + op == 1 + size == 0 + U == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_N = DoubleWordVector(N:Vn) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vhsub.u8 ?dwvec_D dwvec_N dwvec_M + + } + + @syntax { + + @subid 1295 + + @assert { + + Q == 0 + op == 1 + size == 1 + U == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_N = DoubleWordVector(N:Vn) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vhsub.u16 ?dwvec_D dwvec_N dwvec_M + + } + + @syntax { + + @subid 1296 + + @assert { + + Q == 0 + op == 1 + size == 10 + U == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_N = DoubleWordVector(N:Vn) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vhsub.u32 ?dwvec_D dwvec_N dwvec_M + + } + +} + +@encoding (A1) { + + @word 1 1 1 U(1) 1 1 1 1 0 D(1) size(2) Vn(4) Vd(4) 0 0 op(1) 0 N(1) Q(1) M(1) 0 Vm(4) + + @syntax { + + @subid 1297 + + @assert { + + Q == 1 + op == 0 + size == 0 + U == 0 + + } + + @conv { + + qwvec_D = QuadWordVector(D:Vd) + qwvec_N = QuadWordVector(N:Vn) + qwvec_M = QuadWordVector(M:Vm) + + } + + @asm vhadd.s8 ?qwvec_D qwvec_N qwvec_M + + } + + @syntax { + + @subid 1298 + + @assert { + + Q == 1 + op == 0 + size == 1 + U == 0 + + } + + @conv { + + qwvec_D = QuadWordVector(D:Vd) + qwvec_N = QuadWordVector(N:Vn) + qwvec_M = QuadWordVector(M:Vm) + + } + + @asm vhadd.s16 ?qwvec_D qwvec_N qwvec_M + + } + + @syntax { + + @subid 1299 + + @assert { + + Q == 1 + op == 0 + size == 10 + U == 0 + + } + + @conv { + + qwvec_D = QuadWordVector(D:Vd) + qwvec_N = QuadWordVector(N:Vn) + qwvec_M = QuadWordVector(M:Vm) + + } + + @asm vhadd.s32 ?qwvec_D qwvec_N qwvec_M + + } + + @syntax { + + @subid 1300 + + @assert { + + Q == 1 + op == 0 + size == 0 + U == 1 + + } + + @conv { + + qwvec_D = QuadWordVector(D:Vd) + qwvec_N = QuadWordVector(N:Vn) + qwvec_M = QuadWordVector(M:Vm) + + } + + @asm vhadd.u8 ?qwvec_D qwvec_N qwvec_M + + } + + @syntax { + + @subid 1301 + + @assert { + + Q == 1 + op == 0 + size == 1 + U == 1 + + } + + @conv { + + qwvec_D = QuadWordVector(D:Vd) + qwvec_N = QuadWordVector(N:Vn) + qwvec_M = QuadWordVector(M:Vm) + + } + + @asm vhadd.u16 ?qwvec_D qwvec_N qwvec_M + + } + + @syntax { + + @subid 1302 + + @assert { + + Q == 1 + op == 0 + size == 10 + U == 1 + + } + + @conv { + + qwvec_D = QuadWordVector(D:Vd) + qwvec_N = QuadWordVector(N:Vn) + qwvec_M = QuadWordVector(M:Vm) + + } + + @asm vhadd.u32 ?qwvec_D qwvec_N qwvec_M + + } + + @syntax { + + @subid 1303 + + @assert { + + Q == 1 + op == 1 + size == 0 + U == 0 + + } + + @conv { + + qwvec_D = QuadWordVector(D:Vd) + qwvec_N = QuadWordVector(N:Vn) + qwvec_M = QuadWordVector(M:Vm) + + } + + @asm vhsub.s8 ?qwvec_D qwvec_N qwvec_M + + } + + @syntax { + + @subid 1304 + + @assert { + + Q == 1 + op == 1 + size == 1 + U == 0 + + } + + @conv { + + qwvec_D = QuadWordVector(D:Vd) + qwvec_N = QuadWordVector(N:Vn) + qwvec_M = QuadWordVector(M:Vm) + + } + + @asm vhsub.s16 ?qwvec_D qwvec_N qwvec_M + + } + + @syntax { + + @subid 1305 + + @assert { + + Q == 1 + op == 1 + size == 10 + U == 0 + + } + + @conv { + + qwvec_D = QuadWordVector(D:Vd) + qwvec_N = QuadWordVector(N:Vn) + qwvec_M = QuadWordVector(M:Vm) + + } + + @asm vhsub.s32 ?qwvec_D qwvec_N qwvec_M + + } + + @syntax { + + @subid 1306 + + @assert { + + Q == 1 + op == 1 + size == 0 + U == 1 + + } + + @conv { + + qwvec_D = QuadWordVector(D:Vd) + qwvec_N = QuadWordVector(N:Vn) + qwvec_M = QuadWordVector(M:Vm) + + } + + @asm vhsub.u8 ?qwvec_D qwvec_N qwvec_M + + } + + @syntax { + + @subid 1307 + + @assert { + + Q == 1 + op == 1 + size == 1 + U == 1 + + } + + @conv { + + qwvec_D = QuadWordVector(D:Vd) + qwvec_N = QuadWordVector(N:Vn) + qwvec_M = QuadWordVector(M:Vm) + + } + + @asm vhsub.u16 ?qwvec_D qwvec_N qwvec_M + + } + + @syntax { + + @subid 1308 + + @assert { + + Q == 1 + op == 1 + size == 10 + U == 1 + + } + + @conv { + + qwvec_D = QuadWordVector(D:Vd) + qwvec_N = QuadWordVector(N:Vn) + qwvec_M = QuadWordVector(M:Vm) + + } + + @asm vhsub.u32 ?qwvec_D qwvec_N qwvec_M + + } + + @syntax { + + @subid 1309 + + @assert { + + Q == 0 + op == 0 + size == 0 + U == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_N = DoubleWordVector(N:Vn) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vhadd.s8 ?dwvec_D dwvec_N dwvec_M + + } + + @syntax { + + @subid 1310 + + @assert { + + Q == 0 + op == 0 + size == 1 + U == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_N = DoubleWordVector(N:Vn) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vhadd.s16 ?dwvec_D dwvec_N dwvec_M + + } + + @syntax { + + @subid 1311 + + @assert { + + Q == 0 + op == 0 + size == 10 + U == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_N = DoubleWordVector(N:Vn) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vhadd.s32 ?dwvec_D dwvec_N dwvec_M + + } + + @syntax { + + @subid 1312 + + @assert { + + Q == 0 + op == 0 + size == 0 + U == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_N = DoubleWordVector(N:Vn) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vhadd.u8 ?dwvec_D dwvec_N dwvec_M + + } + + @syntax { + + @subid 1313 + + @assert { + + Q == 0 + op == 0 + size == 1 + U == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_N = DoubleWordVector(N:Vn) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vhadd.u16 ?dwvec_D dwvec_N dwvec_M + + } + + @syntax { + + @subid 1314 + + @assert { + + Q == 0 + op == 0 + size == 10 + U == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_N = DoubleWordVector(N:Vn) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vhadd.u32 ?dwvec_D dwvec_N dwvec_M + + } + + @syntax { + + @subid 1315 + + @assert { + + Q == 0 + op == 1 + size == 0 + U == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_N = DoubleWordVector(N:Vn) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vhsub.s8 ?dwvec_D dwvec_N dwvec_M + + } + + @syntax { + + @subid 1316 + + @assert { + + Q == 0 + op == 1 + size == 1 + U == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_N = DoubleWordVector(N:Vn) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vhsub.s16 ?dwvec_D dwvec_N dwvec_M + + } + + @syntax { + + @subid 1317 + + @assert { + + Q == 0 + op == 1 + size == 10 + U == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_N = DoubleWordVector(N:Vn) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vhsub.s32 ?dwvec_D dwvec_N dwvec_M + + } + + @syntax { + + @subid 1318 + + @assert { + + Q == 0 + op == 1 + size == 0 + U == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_N = DoubleWordVector(N:Vn) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vhsub.u8 ?dwvec_D dwvec_N dwvec_M + + } + + @syntax { + + @subid 1319 + + @assert { + + Q == 0 + op == 1 + size == 1 + U == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_N = DoubleWordVector(N:Vn) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vhsub.u16 ?dwvec_D dwvec_N dwvec_M + + } + + @syntax { + + @subid 1320 + + @assert { + + Q == 0 + op == 1 + size == 10 + U == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_N = DoubleWordVector(N:Vn) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vhsub.u32 ?dwvec_D dwvec_N dwvec_M + + } + +} + |