summaryrefslogtreecommitdiff
path: root/plugins/arm/v7/opdefs/A88336_vmla.d
diff options
context:
space:
mode:
Diffstat (limited to 'plugins/arm/v7/opdefs/A88336_vmla.d')
-rw-r--r--plugins/arm/v7/opdefs/A88336_vmla.d1209
1 files changed, 1209 insertions, 0 deletions
diff --git a/plugins/arm/v7/opdefs/A88336_vmla.d b/plugins/arm/v7/opdefs/A88336_vmla.d
new file mode 100644
index 0000000..93f0161
--- /dev/null
+++ b/plugins/arm/v7/opdefs/A88336_vmla.d
@@ -0,0 +1,1209 @@
+
+/* Chrysalide - Outil d'analyse de fichiers binaires
+ * ##FILE## - traduction d'instructions ARMv7
+ *
+ * Copyright (C) 2017 Cyrille Bagard
+ *
+ * This file is part of Chrysalide.
+ *
+ * Chrysalide is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * Chrysalide is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with Chrysalide. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+@title VMLA, VMLAL, VMLS, VMLSL (integer)
+
+@id 314
+
+@desc {
+
+ Vector Multiply Accumulate and Vector Multiply Subtract multiply corresponding elements in two vectors, and either add the products to, or subtract them from, the corresponding elements of the destination vector. Vector Multiply Accumulate Long and Vector Multiply Subtract Long do the same thing, but with destination vector elements that are twice as long as the elements that are multiplied. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. Summary of access controls for Advanced SIMD functionality on page B1-1232 summarizes these controls. ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available as a VFP instruction encoding, see Conditional execution on page A8-288.
+
+}
+
+@encoding (T1) {
+
+ @word 1 1 1 op(1) 1 1 1 1 0 D(1) size(2) Vn(4) Vd(4) 1 0 0 1 N(1) Q(1) M(1) 0 Vm(4)
+
+ @syntax {
+
+ @subid 1429
+
+ @assert {
+
+ Q == 1
+ op == 0
+ size == 0
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_N = QuadWordVector(N:Vn)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vmla.i8 qwvec_D qwvec_N qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1430
+
+ @assert {
+
+ Q == 1
+ op == 0
+ size == 1
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_N = QuadWordVector(N:Vn)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vmla.i16 qwvec_D qwvec_N qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1431
+
+ @assert {
+
+ Q == 1
+ op == 0
+ size == 10
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_N = QuadWordVector(N:Vn)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vmla.i32 qwvec_D qwvec_N qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1432
+
+ @assert {
+
+ Q == 1
+ op == 1
+ size == 0
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_N = QuadWordVector(N:Vn)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vmls.i8 qwvec_D qwvec_N qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1433
+
+ @assert {
+
+ Q == 1
+ op == 1
+ size == 1
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_N = QuadWordVector(N:Vn)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vmls.i16 qwvec_D qwvec_N qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1434
+
+ @assert {
+
+ Q == 1
+ op == 1
+ size == 10
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_N = QuadWordVector(N:Vn)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vmls.i32 qwvec_D qwvec_N qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1435
+
+ @assert {
+
+ Q == 0
+ op == 0
+ size == 0
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmla.i8 dwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1436
+
+ @assert {
+
+ Q == 0
+ op == 0
+ size == 1
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmla.i16 dwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1437
+
+ @assert {
+
+ Q == 0
+ op == 0
+ size == 10
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmla.i32 dwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1438
+
+ @assert {
+
+ Q == 0
+ op == 1
+ size == 0
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmls.i8 dwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1439
+
+ @assert {
+
+ Q == 0
+ op == 1
+ size == 1
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmls.i16 dwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1440
+
+ @assert {
+
+ Q == 0
+ op == 1
+ size == 10
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmls.i32 dwvec_D dwvec_N dwvec_M
+
+ }
+
+}
+
+@encoding (T2) {
+
+ @word 1 1 1 U(1) 1 1 1 1 1 D(1) size(2) Vn(4) Vd(4) 1 0 op(1) 0 N(1) 0 M(1) 0 Vm(4)
+
+ @syntax {
+
+ @subid 1441
+
+ @assert {
+
+ op == 0
+ U == 0
+ size == 0
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmlal.s8 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1442
+
+ @assert {
+
+ op == 0
+ U == 0
+ size == 1
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmlal.s16 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1443
+
+ @assert {
+
+ op == 0
+ U == 0
+ size == 10
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmlal.s32 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1444
+
+ @assert {
+
+ op == 0
+ U == 1
+ size == 0
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmlal.u8 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1445
+
+ @assert {
+
+ op == 0
+ U == 1
+ size == 1
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmlal.u16 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1446
+
+ @assert {
+
+ op == 0
+ U == 1
+ size == 10
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmlal.u32 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1447
+
+ @assert {
+
+ op == 1
+ U == 0
+ size == 0
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmlsl.s8 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1448
+
+ @assert {
+
+ op == 1
+ U == 0
+ size == 1
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmlsl.s16 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1449
+
+ @assert {
+
+ op == 1
+ U == 0
+ size == 10
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmlsl.s32 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1450
+
+ @assert {
+
+ op == 1
+ U == 1
+ size == 0
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmlsl.u8 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1451
+
+ @assert {
+
+ op == 1
+ U == 1
+ size == 1
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmlsl.u16 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1452
+
+ @assert {
+
+ op == 1
+ U == 1
+ size == 10
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmlsl.u32 qwvec_D dwvec_N dwvec_M
+
+ }
+
+}
+
+@encoding (A1) {
+
+ @word 1 1 1 op(1) 1 1 1 1 0 D(1) size(2) Vn(4) Vd(4) 1 0 0 1 N(1) Q(1) M(1) 0 Vm(4)
+
+ @syntax {
+
+ @subid 1453
+
+ @assert {
+
+ Q == 1
+ op == 0
+ size == 0
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_N = QuadWordVector(N:Vn)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vmla.i8 qwvec_D qwvec_N qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1454
+
+ @assert {
+
+ Q == 1
+ op == 0
+ size == 1
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_N = QuadWordVector(N:Vn)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vmla.i16 qwvec_D qwvec_N qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1455
+
+ @assert {
+
+ Q == 1
+ op == 0
+ size == 10
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_N = QuadWordVector(N:Vn)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vmla.i32 qwvec_D qwvec_N qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1456
+
+ @assert {
+
+ Q == 1
+ op == 1
+ size == 0
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_N = QuadWordVector(N:Vn)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vmls.i8 qwvec_D qwvec_N qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1457
+
+ @assert {
+
+ Q == 1
+ op == 1
+ size == 1
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_N = QuadWordVector(N:Vn)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vmls.i16 qwvec_D qwvec_N qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1458
+
+ @assert {
+
+ Q == 1
+ op == 1
+ size == 10
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_N = QuadWordVector(N:Vn)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vmls.i32 qwvec_D qwvec_N qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1459
+
+ @assert {
+
+ Q == 0
+ op == 0
+ size == 0
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmla.i8 dwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1460
+
+ @assert {
+
+ Q == 0
+ op == 0
+ size == 1
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmla.i16 dwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1461
+
+ @assert {
+
+ Q == 0
+ op == 0
+ size == 10
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmla.i32 dwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1462
+
+ @assert {
+
+ Q == 0
+ op == 1
+ size == 0
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmls.i8 dwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1463
+
+ @assert {
+
+ Q == 0
+ op == 1
+ size == 1
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmls.i16 dwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1464
+
+ @assert {
+
+ Q == 0
+ op == 1
+ size == 10
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmls.i32 dwvec_D dwvec_N dwvec_M
+
+ }
+
+}
+
+@encoding (A2) {
+
+ @word 1 1 1 U(1) 1 1 1 1 1 D(1) size(2) Vn(4) Vd(4) 1 0 op(1) 0 N(1) 0 M(1) 0 Vm(4)
+
+ @syntax {
+
+ @subid 1465
+
+ @assert {
+
+ op == 0
+ U == 0
+ size == 0
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmlal.s8 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1466
+
+ @assert {
+
+ op == 0
+ U == 0
+ size == 1
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmlal.s16 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1467
+
+ @assert {
+
+ op == 0
+ U == 0
+ size == 10
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmlal.s32 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1468
+
+ @assert {
+
+ op == 0
+ U == 1
+ size == 0
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmlal.u8 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1469
+
+ @assert {
+
+ op == 0
+ U == 1
+ size == 1
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmlal.u16 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1470
+
+ @assert {
+
+ op == 0
+ U == 1
+ size == 10
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmlal.u32 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1471
+
+ @assert {
+
+ op == 1
+ U == 0
+ size == 0
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmlsl.s8 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1472
+
+ @assert {
+
+ op == 1
+ U == 0
+ size == 1
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmlsl.s16 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1473
+
+ @assert {
+
+ op == 1
+ U == 0
+ size == 10
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmlsl.s32 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1474
+
+ @assert {
+
+ op == 1
+ U == 1
+ size == 0
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmlsl.u8 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1475
+
+ @assert {
+
+ op == 1
+ U == 1
+ size == 1
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmlsl.u16 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1476
+
+ @assert {
+
+ op == 1
+ U == 1
+ size == 10
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmlsl.u32 qwvec_D dwvec_N dwvec_M
+
+ }
+
+}
+
generated by cgit v0.11.2-87-g4458 at 2024-04-28 19:04:41 (GMT)