summaryrefslogtreecommitdiff
path: root/plugins/arm/v7/opdefs/A88350_vmul.d
diff options
context:
space:
mode:
Diffstat (limited to 'plugins/arm/v7/opdefs/A88350_vmul.d')
-rw-r--r--plugins/arm/v7/opdefs/A88350_vmul.d1065
1 files changed, 1065 insertions, 0 deletions
diff --git a/plugins/arm/v7/opdefs/A88350_vmul.d b/plugins/arm/v7/opdefs/A88350_vmul.d
new file mode 100644
index 0000000..4b1271a
--- /dev/null
+++ b/plugins/arm/v7/opdefs/A88350_vmul.d
@@ -0,0 +1,1065 @@
+
+/* Chrysalide - Outil d'analyse de fichiers binaires
+ * ##FILE## - traduction d'instructions ARMv7
+ *
+ * Copyright (C) 2017 Cyrille Bagard
+ *
+ * This file is part of Chrysalide.
+ *
+ * Chrysalide is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * Chrysalide is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with Chrysalide. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+@title VMUL, VMULL (integer and polynomial)
+
+@id 323
+
+@desc {
+
+ Vector Multiply multiplies corresponding elements in two vectors. Vector Multiply Long does the same thing, but with destination vector elements that are twice as long as the elements that are multiplied. For information about multiplying polynomials see Polynomial arithmetic over {0, 1} on page A2-93. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. Summary of access controls for Advanced SIMD functionality on page B1-1232 summarizes these controls. ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available as a VFP instruction encoding, see Conditional execution on page A8-288.
+
+}
+
+@encoding (T1) {
+
+ @word 1 1 1 op(1) 1 1 1 1 0 D(1) size(2) Vn(4) Vd(4) 1 0 0 1 N(1) Q(1) M(1) 1 Vm(4)
+
+ @syntax {
+
+ @subid 1527
+
+ @assert {
+
+ Q == 1
+ op == 0
+ size == 0
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_N = QuadWordVector(N:Vn)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vmul.i8 ?qwvec_D qwvec_N qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1528
+
+ @assert {
+
+ Q == 1
+ op == 0
+ size == 1
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_N = QuadWordVector(N:Vn)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vmul.i16 ?qwvec_D qwvec_N qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1529
+
+ @assert {
+
+ Q == 1
+ op == 0
+ size == 10
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_N = QuadWordVector(N:Vn)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vmul.i32 ?qwvec_D qwvec_N qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1530
+
+ @assert {
+
+ Q == 1
+ op == 1
+ size == 0
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_N = QuadWordVector(N:Vn)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vmul.p8 ?qwvec_D qwvec_N qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1531
+
+ @assert {
+
+ Q == 1
+ op == 1
+ size == 1
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_N = QuadWordVector(N:Vn)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vmul.p16 ?qwvec_D qwvec_N qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1532
+
+ @assert {
+
+ Q == 1
+ op == 1
+ size == 10
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_N = QuadWordVector(N:Vn)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vmul.p32 ?qwvec_D qwvec_N qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1533
+
+ @assert {
+
+ Q == 0
+ op == 0
+ size == 0
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmul.i8 ?dwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1534
+
+ @assert {
+
+ Q == 0
+ op == 0
+ size == 1
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmul.i16 ?dwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1535
+
+ @assert {
+
+ Q == 0
+ op == 0
+ size == 10
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmul.i32 ?dwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1536
+
+ @assert {
+
+ Q == 0
+ op == 1
+ size == 0
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmul.p8 ?dwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1537
+
+ @assert {
+
+ Q == 0
+ op == 1
+ size == 1
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmul.p16 ?dwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1538
+
+ @assert {
+
+ Q == 0
+ op == 1
+ size == 10
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmul.p32 ?dwvec_D dwvec_N dwvec_M
+
+ }
+
+}
+
+@encoding (T2) {
+
+ @word 1 1 1 U(1) 1 1 1 1 1 D(1) size(2) Vn(4) Vd(4) 1 1 op(1) 0 N(1) 0 M(1) 0 Vm(4)
+
+ @syntax {
+
+ @subid 1539
+
+ @assert {
+
+ op == 0
+ U == 0
+ size == 0
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmull.s8 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1540
+
+ @assert {
+
+ op == 0
+ U == 0
+ size == 1
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmull.s16 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1541
+
+ @assert {
+
+ op == 0
+ U == 0
+ size == 10
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmull.s32 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1542
+
+ @assert {
+
+ op == 0
+ U == 1
+ size == 0
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmull.u8 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1543
+
+ @assert {
+
+ op == 0
+ U == 1
+ size == 1
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmull.u16 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1544
+
+ @assert {
+
+ op == 0
+ U == 1
+ size == 10
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmull.u32 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1545
+
+ @assert {
+
+ op == 1
+ U == 0
+ size == 0
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmull.p8 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1546
+
+ @assert {
+
+ op == 1
+ U == 0
+ size == 1
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmull.p16 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1547
+
+ @assert {
+
+ op == 1
+ U == 0
+ size == 10
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmull.p32 qwvec_D dwvec_N dwvec_M
+
+ }
+
+}
+
+@encoding (A1) {
+
+ @word 1 1 1 op(1) 1 1 1 1 0 D(1) size(2) Vn(4) Vd(4) 1 0 0 1 N(1) Q(1) M(1) 1 Vm(4)
+
+ @syntax {
+
+ @subid 1548
+
+ @assert {
+
+ Q == 1
+ op == 0
+ size == 0
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_N = QuadWordVector(N:Vn)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vmul.i8 ?qwvec_D qwvec_N qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1549
+
+ @assert {
+
+ Q == 1
+ op == 0
+ size == 1
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_N = QuadWordVector(N:Vn)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vmul.i16 ?qwvec_D qwvec_N qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1550
+
+ @assert {
+
+ Q == 1
+ op == 0
+ size == 10
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_N = QuadWordVector(N:Vn)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vmul.i32 ?qwvec_D qwvec_N qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1551
+
+ @assert {
+
+ Q == 1
+ op == 1
+ size == 0
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_N = QuadWordVector(N:Vn)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vmul.p8 ?qwvec_D qwvec_N qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1552
+
+ @assert {
+
+ Q == 1
+ op == 1
+ size == 1
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_N = QuadWordVector(N:Vn)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vmul.p16 ?qwvec_D qwvec_N qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1553
+
+ @assert {
+
+ Q == 1
+ op == 1
+ size == 10
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_N = QuadWordVector(N:Vn)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vmul.p32 ?qwvec_D qwvec_N qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1554
+
+ @assert {
+
+ Q == 0
+ op == 0
+ size == 0
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmul.i8 ?dwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1555
+
+ @assert {
+
+ Q == 0
+ op == 0
+ size == 1
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmul.i16 ?dwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1556
+
+ @assert {
+
+ Q == 0
+ op == 0
+ size == 10
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmul.i32 ?dwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1557
+
+ @assert {
+
+ Q == 0
+ op == 1
+ size == 0
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmul.p8 ?dwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1558
+
+ @assert {
+
+ Q == 0
+ op == 1
+ size == 1
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmul.p16 ?dwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1559
+
+ @assert {
+
+ Q == 0
+ op == 1
+ size == 10
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmul.p32 ?dwvec_D dwvec_N dwvec_M
+
+ }
+
+}
+
+@encoding (A2) {
+
+ @word 1 1 1 U(1) 1 1 1 1 1 D(1) size(2) Vn(4) Vd(4) 1 1 op(1) 0 N(1) 0 M(1) 0 Vm(4)
+
+ @syntax {
+
+ @subid 1560
+
+ @assert {
+
+ op == 0
+ U == 0
+ size == 0
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmull.s8 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1561
+
+ @assert {
+
+ op == 0
+ U == 0
+ size == 1
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmull.s16 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1562
+
+ @assert {
+
+ op == 0
+ U == 0
+ size == 10
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmull.s32 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1563
+
+ @assert {
+
+ op == 0
+ U == 1
+ size == 0
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmull.u8 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1564
+
+ @assert {
+
+ op == 0
+ U == 1
+ size == 1
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmull.u16 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1565
+
+ @assert {
+
+ op == 0
+ U == 1
+ size == 10
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmull.u32 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1566
+
+ @assert {
+
+ op == 1
+ U == 0
+ size == 0
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmull.p8 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1567
+
+ @assert {
+
+ op == 1
+ U == 0
+ size == 1
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmull.p16 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1568
+
+ @assert {
+
+ op == 1
+ U == 0
+ size == 10
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmull.p32 qwvec_D dwvec_N dwvec_M
+
+ }
+
+}
+