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diff --git a/plugins/arm/v7/opdefs/A88353_vmvn.d b/plugins/arm/v7/opdefs/A88353_vmvn.d
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@@ -0,0 +1,1277 @@
+
+/* Chrysalide - Outil d'analyse de fichiers binaires
+ * ##FILE## - traduction d'instructions ARMv7
+ *
+ * Copyright (C) 2017 Cyrille Bagard
+ *
+ * This file is part of Chrysalide.
+ *
+ * Chrysalide is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * Chrysalide is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with Chrysalide. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+@title VMVN (immediate)
+
+@id 325
+
+@desc {
+
+ Vector Bitwise NOT (immediate) places the bitwise inverse of an immediate integer constant into every element of the destination register. For the range of constants available, see One register and a modified immediate value on page A7-269. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. Summary of access controls for Advanced SIMD functionality on page B1-1232 summarizes these controls. ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available as a VFP instruction encoding, see Conditional execution on page A8-288.
+
+}
+
+@encoding (T1) {
+
+ @word 1 1 1 i(1) 1 1 1 1 1 D(1) 0 0 0 imm3(3) Vd(4) cmode(4) 0 Q(1) 1 1 imm4(4)
+
+ @syntax {
+
+ @subid 1577
+
+ @assert {
+
+ Q == 1
+ cmode == 1000
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i16 qwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1578
+
+ @assert {
+
+ Q == 1
+ cmode == 1001
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i16 qwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1579
+
+ @assert {
+
+ Q == 1
+ cmode == 1010
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i16 qwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1580
+
+ @assert {
+
+ Q == 1
+ cmode == 1011
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i16 qwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1581
+
+ @assert {
+
+ Q == 1
+ cmode == 0
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 qwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1582
+
+ @assert {
+
+ Q == 1
+ cmode == 1
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 qwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1583
+
+ @assert {
+
+ Q == 1
+ cmode == 10
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 qwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1584
+
+ @assert {
+
+ Q == 1
+ cmode == 11
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 qwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1585
+
+ @assert {
+
+ Q == 1
+ cmode == 100
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 qwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1586
+
+ @assert {
+
+ Q == 1
+ cmode == 101
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 qwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1587
+
+ @assert {
+
+ Q == 1
+ cmode == 110
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 qwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1588
+
+ @assert {
+
+ Q == 1
+ cmode == 111
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 qwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1589
+
+ @assert {
+
+ Q == 1
+ cmode == 1100
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 qwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1590
+
+ @assert {
+
+ Q == 1
+ cmode == 1101
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 qwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1591
+
+ @assert {
+
+ Q == 0
+ cmode == 1000
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i16 dwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1592
+
+ @assert {
+
+ Q == 0
+ cmode == 1001
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i16 dwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1593
+
+ @assert {
+
+ Q == 0
+ cmode == 1010
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i16 dwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1594
+
+ @assert {
+
+ Q == 0
+ cmode == 1011
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i16 dwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1595
+
+ @assert {
+
+ Q == 0
+ cmode == 0
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 dwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1596
+
+ @assert {
+
+ Q == 0
+ cmode == 1
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 dwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1597
+
+ @assert {
+
+ Q == 0
+ cmode == 10
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 dwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1598
+
+ @assert {
+
+ Q == 0
+ cmode == 11
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 dwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1599
+
+ @assert {
+
+ Q == 0
+ cmode == 100
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 dwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1600
+
+ @assert {
+
+ Q == 0
+ cmode == 101
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 dwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1601
+
+ @assert {
+
+ Q == 0
+ cmode == 110
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 dwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1602
+
+ @assert {
+
+ Q == 0
+ cmode == 111
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 dwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1603
+
+ @assert {
+
+ Q == 0
+ cmode == 1100
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 dwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1604
+
+ @assert {
+
+ Q == 0
+ cmode == 1101
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 dwvec_D imm64
+
+ }
+
+}
+
+@encoding (A1) {
+
+ @word 1 1 1 i(1) 1 1 1 1 1 D(1) 0 0 0 imm3(3) Vd(4) cmode(4) 0 Q(1) 1 1 imm4(4)
+
+ @syntax {
+
+ @subid 1605
+
+ @assert {
+
+ Q == 1
+ cmode == 1000
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i16 qwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1606
+
+ @assert {
+
+ Q == 1
+ cmode == 1001
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i16 qwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1607
+
+ @assert {
+
+ Q == 1
+ cmode == 1010
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i16 qwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1608
+
+ @assert {
+
+ Q == 1
+ cmode == 1011
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i16 qwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1609
+
+ @assert {
+
+ Q == 1
+ cmode == 0
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 qwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1610
+
+ @assert {
+
+ Q == 1
+ cmode == 1
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 qwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1611
+
+ @assert {
+
+ Q == 1
+ cmode == 10
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 qwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1612
+
+ @assert {
+
+ Q == 1
+ cmode == 11
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 qwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1613
+
+ @assert {
+
+ Q == 1
+ cmode == 100
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 qwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1614
+
+ @assert {
+
+ Q == 1
+ cmode == 101
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 qwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1615
+
+ @assert {
+
+ Q == 1
+ cmode == 110
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 qwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1616
+
+ @assert {
+
+ Q == 1
+ cmode == 111
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 qwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1617
+
+ @assert {
+
+ Q == 1
+ cmode == 1100
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 qwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1618
+
+ @assert {
+
+ Q == 1
+ cmode == 1101
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 qwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1619
+
+ @assert {
+
+ Q == 0
+ cmode == 1000
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i16 dwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1620
+
+ @assert {
+
+ Q == 0
+ cmode == 1001
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i16 dwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1621
+
+ @assert {
+
+ Q == 0
+ cmode == 1010
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i16 dwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1622
+
+ @assert {
+
+ Q == 0
+ cmode == 1011
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i16 dwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1623
+
+ @assert {
+
+ Q == 0
+ cmode == 0
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 dwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1624
+
+ @assert {
+
+ Q == 0
+ cmode == 1
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 dwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1625
+
+ @assert {
+
+ Q == 0
+ cmode == 10
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 dwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1626
+
+ @assert {
+
+ Q == 0
+ cmode == 11
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 dwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1627
+
+ @assert {
+
+ Q == 0
+ cmode == 100
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 dwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1628
+
+ @assert {
+
+ Q == 0
+ cmode == 101
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 dwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1629
+
+ @assert {
+
+ Q == 0
+ cmode == 110
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 dwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1630
+
+ @assert {
+
+ Q == 0
+ cmode == 111
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 dwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1631
+
+ @assert {
+
+ Q == 0
+ cmode == 1100
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 dwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1632
+
+ @assert {
+
+ Q == 0
+ cmode == 1101
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 dwvec_D imm64
+
+ }
+
+}
+
generated by cgit v0.11.2-87-g4458 at 2024-04-28 23:59:37 (GMT)