1 files changed, 1277 insertions, 0 deletions
diff --git a/plugins/arm/v7/opdefs/A88359_vorr.d b/plugins/arm/v7/opdefs/A88359_vorr.d
new file mode 100644
index 0000000..eab567f
--- /dev/null
+++ b/plugins/arm/v7/opdefs/A88359_vorr.d
@@ -0,0 +1,1277 @@
+
+/* Chrysalide - Outil d'analyse de fichiers binaires
+ * ##FILE## - traduction d'instructions ARMv7
+ *
+ * Copyright (C) 2017 Cyrille Bagard
+ *
+ *  This file is part of Chrysalide.
+ *
+ *  Chrysalide is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 3 of the License, or
+ *  (at your option) any later version.
+ *
+ *  Chrysalide is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Chrysalide.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+@title VORR (immediate)
+
+@id 316
+
+@desc {
+
+	This instruction takes the contents of the destination vector, performs a bitwise OR with an immediate constant, and returns the result into the destination vector. For the range of constants available, see One register and a modified immediate value on page A7-269. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. Summary of access controls for Advanced SIMD functionality on page B1-1232 summarizes these controls. ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available as a VFP instruction encoding, see Conditional execution on page A8-288.
+
+}
+
+@encoding (T1) {
+
+	@word 1 1 1 i(1) 1 1 1 1 1 D(1) 0 0 0 imm3(3) Vd(4) cmode(4) 0 Q(1) 0 1 imm4(4)
+
+	@syntax {
+
+		@subid 1453
+
+		@assert {
+
+			Q == 1
+			cmode == 1000
+
+		}
+
+		@conv {
+
+			qwvec_D = QuadWordVector(D:Vd)
+			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)
+
+		}
+
+		@asm vorr.i16 qwvec_D imm64
+
+	}
+
+	@syntax {
+
+		@subid 1454
+
+		@assert {
+
+			Q == 1
+			cmode == 1001
+
+		}
+
+		@conv {
+
+			qwvec_D = QuadWordVector(D:Vd)
+			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)
+
+		}
+
+		@asm vorr.i16 qwvec_D imm64
+
+	}
+
+	@syntax {
+
+		@subid 1455
+
+		@assert {
+
+			Q == 1
+			cmode == 1010
+
+		}
+
+		@conv {
+
+			qwvec_D = QuadWordVector(D:Vd)
+			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)
+
+		}
+
+		@asm vorr.i16 qwvec_D imm64
+
+	}
+
+	@syntax {
+
+		@subid 1456
+
+		@assert {
+
+			Q == 1
+			cmode == 1011
+
+		}
+
+		@conv {
+
+			qwvec_D = QuadWordVector(D:Vd)
+			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)
+
+		}
+
+		@asm vorr.i16 qwvec_D imm64
+
+	}
+
+	@syntax {
+
+		@subid 1457
+
+		@assert {
+
+			Q == 1
+			cmode == 0
+
+		}
+
+		@conv {
+
+			qwvec_D = QuadWordVector(D:Vd)
+			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)
+
+		}
+
+		@asm vorr.i32 qwvec_D imm64
+
+	}
+
+	@syntax {
+
+		@subid 1458
+
+		@assert {
+
+			Q == 1
+			cmode == 1
+
+		}
+
+		@conv {
+
+			qwvec_D = QuadWordVector(D:Vd)
+			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)
+
+		}
+
+		@asm vorr.i32 qwvec_D imm64
+
+	}
+
+	@syntax {
+
+		@subid 1459
+
+		@assert {
+
+			Q == 1
+			cmode == 10
+
+		}
+
+		@conv {
+
+			qwvec_D = QuadWordVector(D:Vd)
+			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)
+
+		}
+
+		@asm vorr.i32 qwvec_D imm64
+
+	}
+
+	@syntax {
+
+		@subid 1460
+
+		@assert {
+
+			Q == 1
+			cmode == 11
+
+		}
+
+		@conv {
+
+			qwvec_D = QuadWordVector(D:Vd)
+			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)
+
+		}
+
+		@asm vorr.i32 qwvec_D imm64
+
+	}
+
+	@syntax {
+
+		@subid 1461
+
+		@assert {
+
+			Q == 1
+			cmode == 100
+
+		}
+
+		@conv {
+
+			qwvec_D = QuadWordVector(D:Vd)
+			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)
+
+		}
+
+		@asm vorr.i32 qwvec_D imm64
+
+	}
+
+	@syntax {
+
+		@subid 1462
+
+		@assert {
+
+			Q == 1
+			cmode == 101
+
+		}
+
+		@conv {
+
+			qwvec_D = QuadWordVector(D:Vd)
+			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)
+
+		}
+
+		@asm vorr.i32 qwvec_D imm64
+
+	}
+
+	@syntax {
+
+		@subid 1463
+
+		@assert {
+
+			Q == 1
+			cmode == 110
+
+		}
+
+		@conv {
+
+			qwvec_D = QuadWordVector(D:Vd)
+			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)
+
+		}
+
+		@asm vorr.i32 qwvec_D imm64
+
+	}
+
+	@syntax {
+
+		@subid 1464
+
+		@assert {
+
+			Q == 1
+			cmode == 111
+
+		}
+
+		@conv {
+
+			qwvec_D = QuadWordVector(D:Vd)
+			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)
+
+		}
+
+		@asm vorr.i32 qwvec_D imm64
+
+	}
+
+	@syntax {
+
+		@subid 1465
+
+		@assert {
+
+			Q == 1
+			cmode == 1100
+
+		}
+
+		@conv {
+
+			qwvec_D = QuadWordVector(D:Vd)
+			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)
+
+		}
+
+		@asm vorr.i32 qwvec_D imm64
+
+	}
+
+	@syntax {
+
+		@subid 1466
+
+		@assert {
+
+			Q == 1
+			cmode == 1101
+
+		}
+
+		@conv {
+
+			qwvec_D = QuadWordVector(D:Vd)
+			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)
+
+		}
+
+		@asm vorr.i32 qwvec_D imm64
+
+	}
+
+	@syntax {
+
+		@subid 1467
+
+		@assert {
+
+			Q == 0
+			cmode == 1000
+
+		}
+
+		@conv {
+
+			dwvec_D = DoubleWordVector(D:Vd)
+			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)
+
+		}
+
+		@asm vorr.i16 dwvec_D imm64
+
+	}
+
+	@syntax {
+
+		@subid 1468
+
+		@assert {
+
+			Q == 0
+			cmode == 1001
+
+		}
+
+		@conv {
+
+			dwvec_D = DoubleWordVector(D:Vd)
+			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)
+
+		}
+
+		@asm vorr.i16 dwvec_D imm64
+
+	}
+
+	@syntax {
+
+		@subid 1469
+
+		@assert {
+
+			Q == 0
+			cmode == 1010
+
+		}
+
+		@conv {
+
+			dwvec_D = DoubleWordVector(D:Vd)
+			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)
+
+		}
+
+		@asm vorr.i16 dwvec_D imm64
+
+	}
+
+	@syntax {
+
+		@subid 1470
+
+		@assert {
+
+			Q == 0
+			cmode == 1011
+
+		}
+
+		@conv {
+
+			dwvec_D = DoubleWordVector(D:Vd)
+			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)
+
+		}
+
+		@asm vorr.i16 dwvec_D imm64
+
+	}
+
+	@syntax {
+
+		@subid 1471
+
+		@assert {
+
+			Q == 0
+			cmode == 0
+
+		}
+
+		@conv {
+
+			dwvec_D = DoubleWordVector(D:Vd)
+			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)
+
+		}
+
+		@asm vorr.i32 dwvec_D imm64
+
+	}
+
+	@syntax {
+
+		@subid 1472
+
+		@assert {
+
+			Q == 0
+			cmode == 1
+
+		}
+
+		@conv {
+
+			dwvec_D = DoubleWordVector(D:Vd)
+			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)
+
+		}
+
+		@asm vorr.i32 dwvec_D imm64
+
+	}
+
+	@syntax {
+
+		@subid 1473
+
+		@assert {
+
+			Q == 0
+			cmode == 10
+
+		}
+
+		@conv {
+
+			dwvec_D = DoubleWordVector(D:Vd)
+			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)
+
+		}
+
+		@asm vorr.i32 dwvec_D imm64
+
+	}
+
+	@syntax {
+
+		@subid 1474
+
+		@assert {
+
+			Q == 0
+			cmode == 11
+
+		}
+
+		@conv {
+
+			dwvec_D = DoubleWordVector(D:Vd)
+			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)
+
+		}
+
+		@asm vorr.i32 dwvec_D imm64
+
+	}
+
+	@syntax {
+
+		@subid 1475
+
+		@assert {
+
+			Q == 0
+			cmode == 100
+
+		}
+
+		@conv {
+
+			dwvec_D = DoubleWordVector(D:Vd)
+			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)
+
+		}
+
+		@asm vorr.i32 dwvec_D imm64
+
+	}
+
+	@syntax {
+
+		@subid 1476
+
+		@assert {
+
+			Q == 0
+			cmode == 101
+
+		}
+
+		@conv {
+
+			dwvec_D = DoubleWordVector(D:Vd)
+			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)
+
+		}
+
+		@asm vorr.i32 dwvec_D imm64
+
+	}
+
+	@syntax {
+
+		@subid 1477
+
+		@assert {
+
+			Q == 0
+			cmode == 110
+
+		}
+
+		@conv {
+
+			dwvec_D = DoubleWordVector(D:Vd)
+			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)
+
+		}
+
+		@asm vorr.i32 dwvec_D imm64
+
+	}
+
+	@syntax {
+
+		@subid 1478
+
+		@assert {
+
+			Q == 0
+			cmode == 111
+
+		}
+
+		@conv {
+
+			dwvec_D = DoubleWordVector(D:Vd)
+			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)
+
+		}
+
+		@asm vorr.i32 dwvec_D imm64
+
+	}
+
+	@syntax {
+
+		@subid 1479
+
+		@assert {
+
+			Q == 0
+			cmode == 1100
+
+		}
+
+		@conv {
+
+			dwvec_D = DoubleWordVector(D:Vd)
+			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)
+
+		}
+
+		@asm vorr.i32 dwvec_D imm64
+
+	}
+
+	@syntax {
+
+		@subid 1480
+
+		@assert {
+
+			Q == 0
+			cmode == 1101
+
+		}
+
+		@conv {
+
+			dwvec_D = DoubleWordVector(D:Vd)
+			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)
+
+		}
+
+		@asm vorr.i32 dwvec_D imm64
+
+	}
+
+}
+
+@encoding (A1) {
+
+	@word 1 1 1 i(1) 1 1 1 1 1 D(1) 0 0 0 imm3(3) Vd(4) cmode(4) 0 Q(1) 0 1 imm4(4)
+
+	@syntax {
+
+		@subid 1481
+
+		@assert {
+
+			Q == 1
+			cmode == 1000
+
+		}
+
+		@conv {
+
+			qwvec_D = QuadWordVector(D:Vd)
+			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)
+
+		}
+
+		@asm vorr.i16 qwvec_D imm64
+
+	}
+
+	@syntax {
+
+		@subid 1482
+
+		@assert {
+
+			Q == 1
+			cmode == 1001
+
+		}
+
+		@conv {
+
+			qwvec_D = QuadWordVector(D:Vd)
+			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)
+
+		}
+
+		@asm vorr.i16 qwvec_D imm64
+
+	}
+
+	@syntax {
+
+		@subid 1483
+
+		@assert {
+
+			Q == 1
+			cmode == 1010
+
+		}
+
+		@conv {
+
+			qwvec_D = QuadWordVector(D:Vd)
+			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)
+
+		}
+
+		@asm vorr.i16 qwvec_D imm64
+
+	}
+
+	@syntax {
+
+		@subid 1484
+
+		@assert {
+
+			Q == 1
+			cmode == 1011
+
+		}
+
+		@conv {
+
+			qwvec_D = QuadWordVector(D:Vd)
+			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)
+
+		}
+
+		@asm vorr.i16 qwvec_D imm64
+
+	}
+
+	@syntax {
+
+		@subid 1485
+
+		@assert {
+
+			Q == 1
+			cmode == 0
+
+		}
+
+		@conv {
+
+			qwvec_D = QuadWordVector(D:Vd)
+			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)
+
+		}
+
+		@asm vorr.i32 qwvec_D imm64
+
+	}
+
+	@syntax {
+
+		@subid 1486
+
+		@assert {
+
+			Q == 1
+			cmode == 1
+
+		}
+
+		@conv {
+
+			qwvec_D = QuadWordVector(D:Vd)
+			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)
+
+		}
+
+		@asm vorr.i32 qwvec_D imm64
+
+	}
+
+	@syntax {
+
+		@subid 1487
+
+		@assert {
+
+			Q == 1
+			cmode == 10
+
+		}
+
+		@conv {
+
+			qwvec_D = QuadWordVector(D:Vd)
+			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)
+
+		}
+
+		@asm vorr.i32 qwvec_D imm64
+
+	}
+
+	@syntax {
+
+		@subid 1488
+
+		@assert {
+
+			Q == 1
+			cmode == 11
+
+		}
+
+		@conv {
+
+			qwvec_D = QuadWordVector(D:Vd)
+			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)
+
+		}
+
+		@asm vorr.i32 qwvec_D imm64
+
+	}
+
+	@syntax {
+
+		@subid 1489
+
+		@assert {
+
+			Q == 1
+			cmode == 100
+
+		}
+
+		@conv {
+
+			qwvec_D = QuadWordVector(D:Vd)
+			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)
+
+		}
+
+		@asm vorr.i32 qwvec_D imm64
+
+	}
+
+	@syntax {
+
+		@subid 1490
+
+		@assert {
+
+			Q == 1
+			cmode == 101
+
+		}
+
+		@conv {
+
+			qwvec_D = QuadWordVector(D:Vd)
+			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)
+
+		}
+
+		@asm vorr.i32 qwvec_D imm64
+
+	}
+
+	@syntax {
+
+		@subid 1491
+
+		@assert {
+
+			Q == 1
+			cmode == 110
+
+		}
+
+		@conv {
+
+			qwvec_D = QuadWordVector(D:Vd)
+			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)
+
+		}
+
+		@asm vorr.i32 qwvec_D imm64
+
+	}
+
+	@syntax {
+
+		@subid 1492
+
+		@assert {
+
+			Q == 1
+			cmode == 111
+
+		}
+
+		@conv {
+
+			qwvec_D = QuadWordVector(D:Vd)
+			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)
+
+		}
+
+		@asm vorr.i32 qwvec_D imm64
+
+	}
+
+	@syntax {
+
+		@subid 1493
+
+		@assert {
+
+			Q == 1
+			cmode == 1100
+
+		}
+
+		@conv {
+
+			qwvec_D = QuadWordVector(D:Vd)
+			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)
+
+		}
+
+		@asm vorr.i32 qwvec_D imm64
+
+	}
+
+	@syntax {
+
+		@subid 1494
+
+		@assert {
+
+			Q == 1
+			cmode == 1101
+
+		}
+
+		@conv {
+
+			qwvec_D = QuadWordVector(D:Vd)
+			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)
+
+		}
+
+		@asm vorr.i32 qwvec_D imm64
+
+	}
+
+	@syntax {
+
+		@subid 1495
+
+		@assert {
+
+			Q == 0
+			cmode == 1000
+
+		}
+
+		@conv {
+
+			dwvec_D = DoubleWordVector(D:Vd)
+			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)
+
+		}
+
+		@asm vorr.i16 dwvec_D imm64
+
+	}
+
+	@syntax {
+
+		@subid 1496
+
+		@assert {
+
+			Q == 0
+			cmode == 1001
+
+		}
+
+		@conv {
+
+			dwvec_D = DoubleWordVector(D:Vd)
+			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)
+
+		}
+
+		@asm vorr.i16 dwvec_D imm64
+
+	}
+
+	@syntax {
+
+		@subid 1497
+
+		@assert {
+
+			Q == 0
+			cmode == 1010
+
+		}
+
+		@conv {
+
+			dwvec_D = DoubleWordVector(D:Vd)
+			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)
+
+		}
+
+		@asm vorr.i16 dwvec_D imm64
+
+	}
+
+	@syntax {
+
+		@subid 1498
+
+		@assert {
+
+			Q == 0
+			cmode == 1011
+
+		}
+
+		@conv {
+
+			dwvec_D = DoubleWordVector(D:Vd)
+			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)
+
+		}
+
+		@asm vorr.i16 dwvec_D imm64
+
+	}
+
+	@syntax {
+
+		@subid 1499
+
+		@assert {
+
+			Q == 0
+			cmode == 0
+
+		}
+
+		@conv {
+
+			dwvec_D = DoubleWordVector(D:Vd)
+			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)
+
+		}
+
+		@asm vorr.i32 dwvec_D imm64
+
+	}
+
+	@syntax {
+
+		@subid 1500
+
+		@assert {
+
+			Q == 0
+			cmode == 1
+
+		}
+
+		@conv {
+
+			dwvec_D = DoubleWordVector(D:Vd)
+			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)
+
+		}
+
+		@asm vorr.i32 dwvec_D imm64
+
+	}
+
+	@syntax {
+
+		@subid 1501
+
+		@assert {
+
+			Q == 0
+			cmode == 10
+
+		}
+
+		@conv {
+
+			dwvec_D = DoubleWordVector(D:Vd)
+			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)
+
+		}
+
+		@asm vorr.i32 dwvec_D imm64
+
+	}
+
+	@syntax {
+
+		@subid 1502
+
+		@assert {
+
+			Q == 0
+			cmode == 11
+
+		}
+
+		@conv {
+
+			dwvec_D = DoubleWordVector(D:Vd)
+			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)
+
+		}
+
+		@asm vorr.i32 dwvec_D imm64
+
+	}
+
+	@syntax {
+
+		@subid 1503
+
+		@assert {
+
+			Q == 0
+			cmode == 100
+
+		}
+
+		@conv {
+
+			dwvec_D = DoubleWordVector(D:Vd)
+			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)
+
+		}
+
+		@asm vorr.i32 dwvec_D imm64
+
+	}
+
+	@syntax {
+
+		@subid 1504
+
+		@assert {
+
+			Q == 0
+			cmode == 101
+
+		}
+
+		@conv {
+
+			dwvec_D = DoubleWordVector(D:Vd)
+			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)
+
+		}
+
+		@asm vorr.i32 dwvec_D imm64
+
+	}
+
+	@syntax {
+
+		@subid 1505
+
+		@assert {
+
+			Q == 0
+			cmode == 110
+
+		}
+
+		@conv {
+
+			dwvec_D = DoubleWordVector(D:Vd)
+			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)
+
+		}
+
+		@asm vorr.i32 dwvec_D imm64
+
+	}
+
+	@syntax {
+
+		@subid 1506
+
+		@assert {
+
+			Q == 0
+			cmode == 111
+
+		}
+
+		@conv {
+
+			dwvec_D = DoubleWordVector(D:Vd)
+			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)
+
+		}
+
+		@asm vorr.i32 dwvec_D imm64
+
+	}
+
+	@syntax {
+
+		@subid 1507
+
+		@assert {
+
+			Q == 0
+			cmode == 1100
+
+		}
+
+		@conv {
+
+			dwvec_D = DoubleWordVector(D:Vd)
+			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)
+
+		}
+
+		@asm vorr.i32 dwvec_D imm64
+
+	}
+
+	@syntax {
+
+		@subid 1508
+
+		@assert {
+
+			Q == 0
+			cmode == 1101
+
+		}
+
+		@conv {
+
+			dwvec_D = DoubleWordVector(D:Vd)
+			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)
+
+		}
+
+		@asm vorr.i32 dwvec_D imm64
+
+	}
+
+}
+