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Diffstat (limited to 'plugins/arm/v7/opdefs/A88364_vpaddl.d')
| -rw-r--r-- | plugins/arm/v7/opdefs/A88364_vpaddl.d | 597 |
1 files changed, 597 insertions, 0 deletions
diff --git a/plugins/arm/v7/opdefs/A88364_vpaddl.d b/plugins/arm/v7/opdefs/A88364_vpaddl.d new file mode 100644 index 0000000..d508785 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88364_vpaddl.d @@ -0,0 +1,597 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title VPADDL + +@id 321 + +@desc { + + Vector Pairwise Add Long adds adjacent pairs of elements of two vectors, and places the results in the destination vector. The vectors can be doubleword or quadword. The operand elements can be 8-bit, 16-bit, or 32-bit integers. The result elements are twice the length of the operand elements. Figure A8-4 shows an example of the operation of VPADDL. Dm + + Dd Figure A8-4 VPADDL doubleword operation for data type S16 Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. Summary of access controls for Advanced SIMD functionality on page B1-1232 summarizes these controls. ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available as a VFP instruction encoding, see Conditional execution on page A8-288. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 1 1 1 1 D(1) 1 1 size(2) 0 0 Vd(4) 0 0 1 0 op(1) Q(1) M(1) 0 Vm(4) + + @syntax { + + @subid 1545 + + @assert { + + Q == 1 + size == 0 + op == 0 + + } + + @conv { + + qwvec_D = QuadWordVector(D:Vd) + qwvec_M = QuadWordVector(M:Vm) + + } + + @asm vpaddl.s8 qwvec_D qwvec_M + + } + + @syntax { + + @subid 1546 + + @assert { + + Q == 1 + size == 1 + op == 0 + + } + + @conv { + + qwvec_D = QuadWordVector(D:Vd) + qwvec_M = QuadWordVector(M:Vm) + + } + + @asm vpaddl.s16 qwvec_D qwvec_M + + } + + @syntax { + + @subid 1547 + + @assert { + + Q == 1 + size == 10 + op == 0 + + } + + @conv { + + qwvec_D = QuadWordVector(D:Vd) + qwvec_M = QuadWordVector(M:Vm) + + } + + @asm vpaddl.s32 qwvec_D qwvec_M + + } + + @syntax { + + @subid 1548 + + @assert { + + Q == 1 + size == 0 + op == 1 + + } + + @conv { + + qwvec_D = QuadWordVector(D:Vd) + qwvec_M = QuadWordVector(M:Vm) + + } + + @asm vpaddl.u8 qwvec_D qwvec_M + + } + + @syntax { + + @subid 1549 + + @assert { + + Q == 1 + size == 1 + op == 1 + + } + + @conv { + + qwvec_D = QuadWordVector(D:Vd) + qwvec_M = QuadWordVector(M:Vm) + + } + + @asm vpaddl.u16 qwvec_D qwvec_M + + } + + @syntax { + + @subid 1550 + + @assert { + + Q == 1 + size == 10 + op == 1 + + } + + @conv { + + qwvec_D = QuadWordVector(D:Vd) + qwvec_M = QuadWordVector(M:Vm) + + } + + @asm vpaddl.u32 qwvec_D qwvec_M + + } + + @syntax { + + @subid 1551 + + @assert { + + Q == 0 + size == 0 + op == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vpaddl.s8 dwvec_D dwvec_M + + } + + @syntax { + + @subid 1552 + + @assert { + + Q == 0 + size == 1 + op == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vpaddl.s16 dwvec_D dwvec_M + + } + + @syntax { + + @subid 1553 + + @assert { + + Q == 0 + size == 10 + op == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vpaddl.s32 dwvec_D dwvec_M + + } + + @syntax { + + @subid 1554 + + @assert { + + Q == 0 + size == 0 + op == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vpaddl.u8 dwvec_D dwvec_M + + } + + @syntax { + + @subid 1555 + + @assert { + + Q == 0 + size == 1 + op == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vpaddl.u16 dwvec_D dwvec_M + + } + + @syntax { + + @subid 1556 + + @assert { + + Q == 0 + size == 10 + op == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vpaddl.u32 dwvec_D dwvec_M + + } + +} + +@encoding (A1) { + + @word 1 1 1 1 1 1 1 1 1 D(1) 1 1 size(2) 0 0 Vd(4) 0 0 1 0 op(1) Q(1) M(1) 0 Vm(4) + + @syntax { + + @subid 1557 + + @assert { + + Q == 1 + size == 0 + op == 0 + + } + + @conv { + + qwvec_D = QuadWordVector(D:Vd) + qwvec_M = QuadWordVector(M:Vm) + + } + + @asm vpaddl.s8 qwvec_D qwvec_M + + } + + @syntax { + + @subid 1558 + + @assert { + + Q == 1 + size == 1 + op == 0 + + } + + @conv { + + qwvec_D = QuadWordVector(D:Vd) + qwvec_M = QuadWordVector(M:Vm) + + } + + @asm vpaddl.s16 qwvec_D qwvec_M + + } + + @syntax { + + @subid 1559 + + @assert { + + Q == 1 + size == 10 + op == 0 + + } + + @conv { + + qwvec_D = QuadWordVector(D:Vd) + qwvec_M = QuadWordVector(M:Vm) + + } + + @asm vpaddl.s32 qwvec_D qwvec_M + + } + + @syntax { + + @subid 1560 + + @assert { + + Q == 1 + size == 0 + op == 1 + + } + + @conv { + + qwvec_D = QuadWordVector(D:Vd) + qwvec_M = QuadWordVector(M:Vm) + + } + + @asm vpaddl.u8 qwvec_D qwvec_M + + } + + @syntax { + + @subid 1561 + + @assert { + + Q == 1 + size == 1 + op == 1 + + } + + @conv { + + qwvec_D = QuadWordVector(D:Vd) + qwvec_M = QuadWordVector(M:Vm) + + } + + @asm vpaddl.u16 qwvec_D qwvec_M + + } + + @syntax { + + @subid 1562 + + @assert { + + Q == 1 + size == 10 + op == 1 + + } + + @conv { + + qwvec_D = QuadWordVector(D:Vd) + qwvec_M = QuadWordVector(M:Vm) + + } + + @asm vpaddl.u32 qwvec_D qwvec_M + + } + + @syntax { + + @subid 1563 + + @assert { + + Q == 0 + size == 0 + op == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vpaddl.s8 dwvec_D dwvec_M + + } + + @syntax { + + @subid 1564 + + @assert { + + Q == 0 + size == 1 + op == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vpaddl.s16 dwvec_D dwvec_M + + } + + @syntax { + + @subid 1565 + + @assert { + + Q == 0 + size == 10 + op == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vpaddl.s32 dwvec_D dwvec_M + + } + + @syntax { + + @subid 1566 + + @assert { + + Q == 0 + size == 0 + op == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vpaddl.u8 dwvec_D dwvec_M + + } + + @syntax { + + @subid 1567 + + @assert { + + Q == 0 + size == 1 + op == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vpaddl.u16 dwvec_D dwvec_M + + } + + @syntax { + + @subid 1568 + + @assert { + + Q == 0 + size == 10 + op == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vpaddl.u32 dwvec_D dwvec_M + + } + +} + |