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Diffstat (limited to 'plugins/arm/v7/opdefs/A88382_vqsub.d')
| -rw-r--r-- | plugins/arm/v7/opdefs/A88382_vqsub.d | 813 |
1 files changed, 813 insertions, 0 deletions
diff --git a/plugins/arm/v7/opdefs/A88382_vqsub.d b/plugins/arm/v7/opdefs/A88382_vqsub.d new file mode 100644 index 0000000..3441a1f --- /dev/null +++ b/plugins/arm/v7/opdefs/A88382_vqsub.d @@ -0,0 +1,813 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title VQSUB + +@id 328 + +@desc { + + Vector Saturating Subtract subtracts the elements of the second operand vector from the corresponding elements of the first operand vector, and places the results in the destination vector. Signed and unsigned operations are distinct. The operand and result elements must all be the same type, and can be any one of: • 8-bit, 16-bit, 32-bit, or 64-bit signed integers • 8-bit, 16-bit, 32-bit, or 64-bit unsigned integers. If any of the results overflow, they are saturated. The cumulative saturation bit, FPSCR.QC, is set if saturation occurs. For details see Pseudocode details of saturation on page A2-44. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. Summary of access controls for Advanced SIMD functionality on page B1-1232 summarizes these controls. ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available as a VFP instruction encoding, see Conditional execution on page A8-288. + +} + +@encoding (T1) { + + @word 1 1 1 U(1) 1 1 1 1 0 D(1) size(2) Vn(4) Vd(4) 0 0 1 0 N(1) Q(1) M(1) 1 Vm(4) + + @syntax { + + @subid 1685 + + @assert { + + Q == 1 + U == 0 + size == 0 + + } + + @conv { + + qwvec_D = QuadWordVector(D:Vd) + qwvec_N = QuadWordVector(N:Vn) + qwvec_M = QuadWordVector(M:Vm) + + } + + @asm vqsub.s8 ?qwvec_D qwvec_N qwvec_M + + } + + @syntax { + + @subid 1686 + + @assert { + + Q == 1 + U == 0 + size == 1 + + } + + @conv { + + qwvec_D = QuadWordVector(D:Vd) + qwvec_N = QuadWordVector(N:Vn) + qwvec_M = QuadWordVector(M:Vm) + + } + + @asm vqsub.s16 ?qwvec_D qwvec_N qwvec_M + + } + + @syntax { + + @subid 1687 + + @assert { + + Q == 1 + U == 0 + size == 10 + + } + + @conv { + + qwvec_D = QuadWordVector(D:Vd) + qwvec_N = QuadWordVector(N:Vn) + qwvec_M = QuadWordVector(M:Vm) + + } + + @asm vqsub.s32 ?qwvec_D qwvec_N qwvec_M + + } + + @syntax { + + @subid 1688 + + @assert { + + Q == 1 + U == 0 + size == 11 + + } + + @conv { + + qwvec_D = QuadWordVector(D:Vd) + qwvec_N = QuadWordVector(N:Vn) + qwvec_M = QuadWordVector(M:Vm) + + } + + @asm vqsub.s64 ?qwvec_D qwvec_N qwvec_M + + } + + @syntax { + + @subid 1689 + + @assert { + + Q == 1 + U == 1 + size == 0 + + } + + @conv { + + qwvec_D = QuadWordVector(D:Vd) + qwvec_N = QuadWordVector(N:Vn) + qwvec_M = QuadWordVector(M:Vm) + + } + + @asm vqsub.u8 ?qwvec_D qwvec_N qwvec_M + + } + + @syntax { + + @subid 1690 + + @assert { + + Q == 1 + U == 1 + size == 1 + + } + + @conv { + + qwvec_D = QuadWordVector(D:Vd) + qwvec_N = QuadWordVector(N:Vn) + qwvec_M = QuadWordVector(M:Vm) + + } + + @asm vqsub.u16 ?qwvec_D qwvec_N qwvec_M + + } + + @syntax { + + @subid 1691 + + @assert { + + Q == 1 + U == 1 + size == 10 + + } + + @conv { + + qwvec_D = QuadWordVector(D:Vd) + qwvec_N = QuadWordVector(N:Vn) + qwvec_M = QuadWordVector(M:Vm) + + } + + @asm vqsub.u32 ?qwvec_D qwvec_N qwvec_M + + } + + @syntax { + + @subid 1692 + + @assert { + + Q == 1 + U == 1 + size == 11 + + } + + @conv { + + qwvec_D = QuadWordVector(D:Vd) + qwvec_N = QuadWordVector(N:Vn) + qwvec_M = QuadWordVector(M:Vm) + + } + + @asm vqsub.u64 ?qwvec_D qwvec_N qwvec_M + + } + + @syntax { + + @subid 1693 + + @assert { + + Q == 0 + U == 0 + size == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_N = DoubleWordVector(N:Vn) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vqsub.s8 ?dwvec_D dwvec_N dwvec_M + + } + + @syntax { + + @subid 1694 + + @assert { + + Q == 0 + U == 0 + size == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_N = DoubleWordVector(N:Vn) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vqsub.s16 ?dwvec_D dwvec_N dwvec_M + + } + + @syntax { + + @subid 1695 + + @assert { + + Q == 0 + U == 0 + size == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_N = DoubleWordVector(N:Vn) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vqsub.s32 ?dwvec_D dwvec_N dwvec_M + + } + + @syntax { + + @subid 1696 + + @assert { + + Q == 0 + U == 0 + size == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_N = DoubleWordVector(N:Vn) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vqsub.s64 ?dwvec_D dwvec_N dwvec_M + + } + + @syntax { + + @subid 1697 + + @assert { + + Q == 0 + U == 1 + size == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_N = DoubleWordVector(N:Vn) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vqsub.u8 ?dwvec_D dwvec_N dwvec_M + + } + + @syntax { + + @subid 1698 + + @assert { + + Q == 0 + U == 1 + size == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_N = DoubleWordVector(N:Vn) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vqsub.u16 ?dwvec_D dwvec_N dwvec_M + + } + + @syntax { + + @subid 1699 + + @assert { + + Q == 0 + U == 1 + size == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_N = DoubleWordVector(N:Vn) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vqsub.u32 ?dwvec_D dwvec_N dwvec_M + + } + + @syntax { + + @subid 1700 + + @assert { + + Q == 0 + U == 1 + size == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_N = DoubleWordVector(N:Vn) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vqsub.u64 ?dwvec_D dwvec_N dwvec_M + + } + +} + +@encoding (A1) { + + @word 1 1 1 U(1) 1 1 1 1 0 D(1) size(2) Vn(4) Vd(4) 0 0 1 0 N(1) Q(1) M(1) 1 Vm(4) + + @syntax { + + @subid 1701 + + @assert { + + Q == 1 + U == 0 + size == 0 + + } + + @conv { + + qwvec_D = QuadWordVector(D:Vd) + qwvec_N = QuadWordVector(N:Vn) + qwvec_M = QuadWordVector(M:Vm) + + } + + @asm vqsub.s8 ?qwvec_D qwvec_N qwvec_M + + } + + @syntax { + + @subid 1702 + + @assert { + + Q == 1 + U == 0 + size == 1 + + } + + @conv { + + qwvec_D = QuadWordVector(D:Vd) + qwvec_N = QuadWordVector(N:Vn) + qwvec_M = QuadWordVector(M:Vm) + + } + + @asm vqsub.s16 ?qwvec_D qwvec_N qwvec_M + + } + + @syntax { + + @subid 1703 + + @assert { + + Q == 1 + U == 0 + size == 10 + + } + + @conv { + + qwvec_D = QuadWordVector(D:Vd) + qwvec_N = QuadWordVector(N:Vn) + qwvec_M = QuadWordVector(M:Vm) + + } + + @asm vqsub.s32 ?qwvec_D qwvec_N qwvec_M + + } + + @syntax { + + @subid 1704 + + @assert { + + Q == 1 + U == 0 + size == 11 + + } + + @conv { + + qwvec_D = QuadWordVector(D:Vd) + qwvec_N = QuadWordVector(N:Vn) + qwvec_M = QuadWordVector(M:Vm) + + } + + @asm vqsub.s64 ?qwvec_D qwvec_N qwvec_M + + } + + @syntax { + + @subid 1705 + + @assert { + + Q == 1 + U == 1 + size == 0 + + } + + @conv { + + qwvec_D = QuadWordVector(D:Vd) + qwvec_N = QuadWordVector(N:Vn) + qwvec_M = QuadWordVector(M:Vm) + + } + + @asm vqsub.u8 ?qwvec_D qwvec_N qwvec_M + + } + + @syntax { + + @subid 1706 + + @assert { + + Q == 1 + U == 1 + size == 1 + + } + + @conv { + + qwvec_D = QuadWordVector(D:Vd) + qwvec_N = QuadWordVector(N:Vn) + qwvec_M = QuadWordVector(M:Vm) + + } + + @asm vqsub.u16 ?qwvec_D qwvec_N qwvec_M + + } + + @syntax { + + @subid 1707 + + @assert { + + Q == 1 + U == 1 + size == 10 + + } + + @conv { + + qwvec_D = QuadWordVector(D:Vd) + qwvec_N = QuadWordVector(N:Vn) + qwvec_M = QuadWordVector(M:Vm) + + } + + @asm vqsub.u32 ?qwvec_D qwvec_N qwvec_M + + } + + @syntax { + + @subid 1708 + + @assert { + + Q == 1 + U == 1 + size == 11 + + } + + @conv { + + qwvec_D = QuadWordVector(D:Vd) + qwvec_N = QuadWordVector(N:Vn) + qwvec_M = QuadWordVector(M:Vm) + + } + + @asm vqsub.u64 ?qwvec_D qwvec_N qwvec_M + + } + + @syntax { + + @subid 1709 + + @assert { + + Q == 0 + U == 0 + size == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_N = DoubleWordVector(N:Vn) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vqsub.s8 ?dwvec_D dwvec_N dwvec_M + + } + + @syntax { + + @subid 1710 + + @assert { + + Q == 0 + U == 0 + size == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_N = DoubleWordVector(N:Vn) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vqsub.s16 ?dwvec_D dwvec_N dwvec_M + + } + + @syntax { + + @subid 1711 + + @assert { + + Q == 0 + U == 0 + size == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_N = DoubleWordVector(N:Vn) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vqsub.s32 ?dwvec_D dwvec_N dwvec_M + + } + + @syntax { + + @subid 1712 + + @assert { + + Q == 0 + U == 0 + size == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_N = DoubleWordVector(N:Vn) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vqsub.s64 ?dwvec_D dwvec_N dwvec_M + + } + + @syntax { + + @subid 1713 + + @assert { + + Q == 0 + U == 1 + size == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_N = DoubleWordVector(N:Vn) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vqsub.u8 ?dwvec_D dwvec_N dwvec_M + + } + + @syntax { + + @subid 1714 + + @assert { + + Q == 0 + U == 1 + size == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_N = DoubleWordVector(N:Vn) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vqsub.u16 ?dwvec_D dwvec_N dwvec_M + + } + + @syntax { + + @subid 1715 + + @assert { + + Q == 0 + U == 1 + size == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_N = DoubleWordVector(N:Vn) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vqsub.u32 ?dwvec_D dwvec_N dwvec_M + + } + + @syntax { + + @subid 1716 + + @assert { + + Q == 0 + U == 1 + size == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_N = DoubleWordVector(N:Vn) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vqsub.u64 ?dwvec_D dwvec_N dwvec_M + + } + +} + |