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+
+/* Chrysalide - Outil d'analyse de fichiers binaires
+ * ##FILE## - traduction d'instructions ARMv7
+ *
+ * Copyright (C) 2017 Cyrille Bagard
+ *
+ * This file is part of Chrysalide.
+ *
+ * Chrysalide is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * Chrysalide is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with Chrysalide. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+@title VREV16, VREV32, VREV64
+
+@id 332
+
+@desc {
+
+ VREV16 (Vector Reverse in halfwords) reverses the order of 8-bit elements in each halfword of the vector, and places the result in the corresponding destination vector. VREV32 (Vector Reverse in words) reverses the order of 8-bit or 16-bit elements in each word of the vector, and places the result in the corresponding destination vector. VREV64 (Vector Reverse in doublewords) reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector, and places the result in the corresponding destination vector. There is no distinction between data types, other than size. Figure A8-6 shows two examples of the operation of VREV. VREV64.8, doubleword VREV64.32, quadword Dm Qm Dd Qm Figure A8-6 VREV operation examples Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. Summary of access controls for Advanced SIMD functionality on page B1-1232 summarizes these controls. ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available as a VFP instruction encoding, see Conditional execution on page A8-288.
+
+}
+
+@encoding (T1) {
+
+ @word 1 1 1 1 1 1 1 1 1 D(1) 1 1 size(2) 0 0 Vd(4) 0 0 0 op(2) Q(1) M(1) 0 Vm(4)
+
+ @syntax {
+
+ @subid 1735
+
+ @assert {
+
+ Q == 1
+ op == 10
+ size == 0
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vrev16.8 qwvec_D qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1736
+
+ @assert {
+
+ Q == 1
+ op == 10
+ size == 1
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vrev16.16 qwvec_D qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1737
+
+ @assert {
+
+ Q == 1
+ op == 10
+ size == 10
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vrev16.32 qwvec_D qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1738
+
+ @assert {
+
+ Q == 1
+ op == 1
+ size == 0
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vrev32.8 qwvec_D qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1739
+
+ @assert {
+
+ Q == 1
+ op == 1
+ size == 1
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vrev32.16 qwvec_D qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1740
+
+ @assert {
+
+ Q == 1
+ op == 1
+ size == 10
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vrev32.32 qwvec_D qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1741
+
+ @assert {
+
+ Q == 1
+ op == 0
+ size == 0
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vrev64.8 qwvec_D qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1742
+
+ @assert {
+
+ Q == 1
+ op == 0
+ size == 1
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vrev64.16 qwvec_D qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1743
+
+ @assert {
+
+ Q == 1
+ op == 0
+ size == 10
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vrev64.32 qwvec_D qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1744
+
+ @assert {
+
+ Q == 0
+ op == 10
+ size == 0
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vrev16.8 dwvec_D dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1745
+
+ @assert {
+
+ Q == 0
+ op == 10
+ size == 1
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vrev16.16 dwvec_D dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1746
+
+ @assert {
+
+ Q == 0
+ op == 10
+ size == 10
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vrev16.32 dwvec_D dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1747
+
+ @assert {
+
+ Q == 0
+ op == 1
+ size == 0
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vrev32.8 dwvec_D dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1748
+
+ @assert {
+
+ Q == 0
+ op == 1
+ size == 1
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vrev32.16 dwvec_D dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1749
+
+ @assert {
+
+ Q == 0
+ op == 1
+ size == 10
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vrev32.32 dwvec_D dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1750
+
+ @assert {
+
+ Q == 0
+ op == 0
+ size == 0
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vrev64.8 dwvec_D dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1751
+
+ @assert {
+
+ Q == 0
+ op == 0
+ size == 1
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vrev64.16 dwvec_D dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1752
+
+ @assert {
+
+ Q == 0
+ op == 0
+ size == 10
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vrev64.32 dwvec_D dwvec_M
+
+ }
+
+}
+
+@encoding (A1) {
+
+ @word 1 1 1 1 1 1 1 1 1 D(1) 1 1 size(2) 0 0 Vd(4) 0 0 0 op(2) Q(1) M(1) 0 Vm(4)
+
+ @syntax {
+
+ @subid 1753
+
+ @assert {
+
+ Q == 1
+ op == 10
+ size == 0
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vrev16.8 qwvec_D qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1754
+
+ @assert {
+
+ Q == 1
+ op == 10
+ size == 1
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vrev16.16 qwvec_D qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1755
+
+ @assert {
+
+ Q == 1
+ op == 10
+ size == 10
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vrev16.32 qwvec_D qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1756
+
+ @assert {
+
+ Q == 1
+ op == 1
+ size == 0
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vrev32.8 qwvec_D qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1757
+
+ @assert {
+
+ Q == 1
+ op == 1
+ size == 1
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vrev32.16 qwvec_D qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1758
+
+ @assert {
+
+ Q == 1
+ op == 1
+ size == 10
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vrev32.32 qwvec_D qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1759
+
+ @assert {
+
+ Q == 1
+ op == 0
+ size == 0
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vrev64.8 qwvec_D qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1760
+
+ @assert {
+
+ Q == 1
+ op == 0
+ size == 1
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vrev64.16 qwvec_D qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1761
+
+ @assert {
+
+ Q == 1
+ op == 0
+ size == 10
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vrev64.32 qwvec_D qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1762
+
+ @assert {
+
+ Q == 0
+ op == 10
+ size == 0
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vrev16.8 dwvec_D dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1763
+
+ @assert {
+
+ Q == 0
+ op == 10
+ size == 1
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vrev16.16 dwvec_D dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1764
+
+ @assert {
+
+ Q == 0
+ op == 10
+ size == 10
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vrev16.32 dwvec_D dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1765
+
+ @assert {
+
+ Q == 0
+ op == 1
+ size == 0
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vrev32.8 dwvec_D dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1766
+
+ @assert {
+
+ Q == 0
+ op == 1
+ size == 1
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vrev32.16 dwvec_D dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1767
+
+ @assert {
+
+ Q == 0
+ op == 1
+ size == 10
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vrev32.32 dwvec_D dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1768
+
+ @assert {
+
+ Q == 0
+ op == 0
+ size == 0
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vrev64.8 dwvec_D dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1769
+
+ @assert {
+
+ Q == 0
+ op == 0
+ size == 1
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vrev64.16 dwvec_D dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1770
+
+ @assert {
+
+ Q == 0
+ op == 0
+ size == 10
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vrev64.32 dwvec_D dwvec_M
+
+ }
+
+}
+
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