summaryrefslogtreecommitdiff
path: root/plugins/arm/v7/opdefs/A8865_ldr.d
diff options
context:
space:
mode:
Diffstat (limited to 'plugins/arm/v7/opdefs/A8865_ldr.d')
-rw-r--r--plugins/arm/v7/opdefs/A8865_ldr.d80
1 files changed, 80 insertions, 0 deletions
diff --git a/plugins/arm/v7/opdefs/A8865_ldr.d b/plugins/arm/v7/opdefs/A8865_ldr.d
new file mode 100644
index 0000000..a810586
--- /dev/null
+++ b/plugins/arm/v7/opdefs/A8865_ldr.d
@@ -0,0 +1,80 @@
+
+/* Chrysalide - Outil d'analyse de fichiers binaires
+ * ##FILE## - traduction d'instructions ARMv7
+ *
+ * Copyright (C) 2017 Cyrille Bagard
+ *
+ * This file is part of Chrysalide.
+ *
+ * Chrysalide is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * Chrysalide is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with Chrysalide. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+@title LDR (register, Thumb)
+
+@id 59
+
+@desc {
+
+ Load Register (register) calculates an address from a base register value and an offset register value, loads a word from memory, and writes it to a register. The offset register value can optionally be shifted. For information about memory accesses, see Memory accesses on page A8-294. The Thumb form of LDR (register) does not support register writeback.
+
+}
+
+@encoding (t1) {
+
+ @half 0 1 0 1 1 0 0 Rm(3) Rn(3) Rt(3)
+
+ @syntax {
+
+ @subid 180
+
+ @conv {
+
+ reg_T = Register(Rt)
+ reg_N = Register(Rn)
+ reg_M = Register(Rm)
+ maccess = MemAccessOffset(reg_N, reg_M)
+
+ }
+
+ @asm ldr reg_T maccess
+
+ }
+
+}
+
+@encoding (T2) {
+
+ @word 1 1 1 1 1 0 0 0 0 1 0 1 Rn(4) Rt(4) 0 0 0 0 0 0 imm2(2) Rm(4)
+
+ @syntax {
+
+ @subid 181
+
+ @conv {
+
+ reg_T = Register(Rt)
+ reg_N = Register(Rn)
+ reg_M = Register(Rm)
+ shift = FixedShift(SRType_LSL, imm2)
+ maccess = MemAccessOffsetExtended(reg_N, reg_M, shift)
+
+ }
+
+ @asm ldr.w reg_T maccess
+
+ }
+
+}
+