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Diffstat (limited to 'plugins/arm/v7/opdefs/A8875_ldrex.d')
-rw-r--r-- | plugins/arm/v7/opdefs/A8875_ldrex.d | 85 |
1 files changed, 85 insertions, 0 deletions
diff --git a/plugins/arm/v7/opdefs/A8875_ldrex.d b/plugins/arm/v7/opdefs/A8875_ldrex.d new file mode 100644 index 0000000..39c708c --- /dev/null +++ b/plugins/arm/v7/opdefs/A8875_ldrex.d @@ -0,0 +1,85 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title LDREX + +@id 69 + +@desc { + + Load Register Exclusive calculates an address from a base register value and an immediate offset, loads a word from memory, writes it to a register and: • if the address has the Shared Memory attribute, marks the physical address as exclusive access for the executing processor in a global monitor • causes the executing processor to indicate an active exclusive access in the local monitor. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. + +} + +@encoding (T1) { + + @word 1 1 1 0 1 0 0 0 0 1 0 1 Rn(4) Rt(4) 1 1 1 1 imm8(8) + + @syntax { + + @subid 214 + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm ldrex reg_T maccess + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 1 0 0 1 Rn(4) Rt(4) 1 1 1 1 1 0 0 1 1 1 1 1 + + @syntax { + + @subid 215 + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = Zeros(32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm ldrex reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + |